ICS507M-01 [ICSI]
PECL Clock Synthesizer; PECL时钟合成器
| 型号： | ICS507M-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | PECL Clock Synthesizer |
| 文件： | 总5页 (文件大小：53K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS507-01/02
PECL Clock Synthesizer
Description
Features
The ICS507-01 and ICS507-02 are inexpensive
ways to generate a low jitter 155.52 MHz (or other
high speed) differential PECL clock output from a
low frequency crystal input. Using Phase-Locked-
Loop (PLL) techniques, the devices use a standard
fundamental mode crystal to produce output
clocks up to 200 MHz.
• Packaged as 16 pin narrow SOIC or die
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 5 - 52 MHz
• Uses low-cost crystal
• Differential PECL output clock frequencies up
to 200 MHz
Stored in each chip’s ROM is the ability to
generate a selection of different multiples of the
input reference frequency, including an exact
155.52 MHz clock from common crystals. For
lowest jitter and phase noise on a 155.52 MHz
clock, a 19.44 MHz crystal and the x8 selection
can be used.
• Duty cycle of 49/51
• 3.3 V or 5.0 V±10% operating supply
• Ideal for SONET applications and oscillator
manufacturers
• Advanced, low power CMOS process
• Industrial temperature versions available
Block Diagram
1.1kΩ
GND
VDD
RES
270Ω
Output
2
PECL
S0:1
Buffer
62Ω
Clock Synthesis
and Control
Circuitry
VDD
Crystal
or
clock
X1
X2
Clock
Buffer/
Crystal
62Ω
Output
Buffer
PECL
Oscillator
270Ω
Output resistor values shown are for unterminated lines.
Refer to MAN09 for additional information.
Output Enable
(both outputs)
MDS 507 C
1
Revision 042600
Printed 11/13/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com
ICS507-01/02
PECL Clock Synthesizer
Clock Multiplier Select Table
Pin Assignment
ICS507-01/02
S1
0
S0
0
Multiplier
9.72X*
10X
*Use this selection to get
155.52 MHz from a 16 MHz
input.
0
M
1
16 X2
1
2
3
4
5
6
7
8
X1/ICLK
VDD
0
12X
15
14
N C
S0
For lowest phase noise
generation of 155.52 MHz,
use a 19.44 MHz crystal and
the 8X selection.
M
M
M
1
0
6.25X
8X
VDD
S1
M
1
13 OE
12 N C
11 N C
5X
0
2X
GND
GND
N C
1
M
1
3X
1
4X
RES
10
9
0 = connect pin directly to ground
1 = connect pin directly to VDD
M = leave unconnected (floating)
PECL
PECL
16 pin narrow (150 mil) SOIC
Pin Descriptions
Number
Name
X1/ICLK
VDD
VDD
S1
Type Description
1
2
XI
P
Crystal or clock connection. Connect to a fundamental parallel mode crystal, or clock.
VDD. Connect to +3.3 V or +5 V, and to VDD on pin 3.
VDD. Connect to VDD on pin 2. Decouple with pin 5.
Multiplier select pin 1. Determines output frequency per table above.
Connect to ground.
3
P
4
T I
P
5
GND
GND
NC
6
P
Connect to ground.
7
-
No connect. Nothing is connected internally to this pin.
PECL Output. Connect to resistor load as shown on page one.
Complementary PECL Output. Connect to resistor load as shown on page one.
Bias Resistor Input. Connect a resistor between this pin and VDD.
No connect. Nothing is connected internally to this pin.
No connect. Nothing is connected internally to this pin.
Output Enable. Tri-states both outputs when low. Internal pull-up.
Multiplier select pin 0. Determines output frequency per table above.
No Connect. Nothing is connected internally to this pin.
Cr stal connection. Connect to cr stal, or leave unconnected for clock input.
8
PECL
PECL
RES
NC
O
O
I
9
10
11
12
13
14
15
16
-
NC
-
OE
I
S0
T I
-
NC
X2
XO
Key: I=Input, O=output, TI=tri-level input, P=power supply connection; XI, XO=crystal connections
MDS 507 C
2
Revision 042600
Printed 11/13/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com
ICS507-01/02
PECL Clock Synthesizer
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses be ond these can permanentl damage the device)
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
ICS507M-0x
7
VDD+0.5
VDD+0.5
70
V
V
-0.5
-0.5
0
Clock Output
V
Ambient Operating Temperature
°C
°C
°C
°C
ICS507M-0xI
-40
85
Soldering Temperature
Storage temperature
Max of 20 seconds
260
-65
150
DC CHARACTERISTICS (VDD = 5.0 V unless otherwise noted)
Operating Voltage, VDD
3.0
5.5
V
V
Input High Voltage, VIH
Input Low Voltage, VIL
ICLK only
ICLK only
S0, S1
VDD/2 + 1
VDD/2
VDD/2
VDD/2-1
VDD+0.5
VDD-2.0
V
Input High Voltage, VIH
Input Low Voltage, VIL
VDD-0.5
VDD-1.2
V
S0, S1
V
Output High Voltage, VOH
Output Low Voltage, VOL
IDD Operating Suppl Current, note 3
Internal Cr stal Capacitance, X1 and X2
Input Capacitance
Note 2
V
Note 2
V
No Load, 155.52MHz
Pins 1, 8
67
26
4
mA
pF
pF
S0, S1
AC CHARACTERISTICS (VDD = 5.0 V unless otherwise noted)
Input Crystal Frequency
5
5
27
52
MH z
MH z
MH z
MH z
MH z
MH z
MH z
MH z
%
Input Clock Frequency
Output Frequency, ICS507-01
0 to 70°C VDD = 5.0 V
0 to 70°C VDD = 3.3 V
10
10
10
125
125
125
49
10
200
156
125
200
200
160
51
Output Frequency, ICS507-01I -40 to 85°C VDD = 3.3 V or 5.0 V
Output Frequency, ICS507-02I
0 to 70°C VDD = 5.0 V
0 to 70°C VDD = 3.3 V
-40 to 85°C VDD = 3.3 V or 5.0 V
Output Clock Duty Cycle
PLL Bandwidth
kH z
ps
Absolute Clock Period Jitter
One Sigma Clock Period Jitter
Deviation from mean
±75
20
ps
Notes: 1) All typical values are at 5.0 V and 25°C unless otherwise noted.
2) VOH and VOL can be set by the external resistor values on the PECL outputs.
3) IDD includes the current through the external resistors, which can be modified.
4) The phase relationship between input and output can change at power up. For a fixed phase relationship, see one of the
ICS zero delay buffers.
MDS 507 C
3
Revision 042600
Printed 11/13/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com
ICS507-01/02
PECL Clock Synthesizer
Applications
High Frequency Differential PECL Oscillators: The ICS507 plus a low frequency, fundamental mode
crystal can build a high frequency differential output oscillator. For example, a 10 MHz crystal connected
to the ICS507 with the 12X output selected (S1=0, S0=1) produces a 120 MHz PECL output clock.
High Frequency TCXO: Extending the previous application, an inexpensive, low frequency TCXO can be
built and the output frequency can be multiplied using the ICS507. Since the output of the chip is phase-
locked to the input, the ICS507 has no temperature dependence, and the temperature coefficient of the
combined system is the same as that of the low frequency TCXO.
High Frequency VCXO: The bandwidth of the PLL is guaranteed to be greater than 10 kHz. This means
that the PLL will track any modulation on the input with a frequency of less than 10 kHz. By using this
property, a low frequency VCXO can be built, and the output can then be multiplied with the ICS507 to
give a high frequency output, thereby producing a high frequency VCXO.
Decoupling and External Components
The ICS507 requires a 0.01µF decoupling capacitor to be connected between VDD and GND on pins 2
and 5. It must be connected close to the ICS507. Other VDD and GND connections should be
connected to those pins, or to the VDD and GND planes on the board. A resistor must be connected
between the RES (pin 10) and VDD. Another four resistors are needed for the PECL outputs as shown on
the block diagram on page 1. Suggested values of these resistors are shown in the Block Diagram, but they
can be varied to change the differential pair output swing, and the DC level; refer to MAN09.
MDS 507 C
4
Revision 042600
Printed 11/13/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com
ICS507-01/02
PECL Clock Synthesizer
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
16 pin SOIC narrow
Inches
Min
Millimeters
Symbol
A
Max
Min
1.35
Max
0.0532
0.0040
0.0130
0.0075
0.3859
0.1497
.050 BSC
0.2284
0.0099
0.0160
0.0688
0.0098
0.0200
0.0098
0.3937
0.1574
1.75
0.24
0.51
0.24
10.00
4.00
A1
0.10
B
C
0.33
E
H
0.19
INDEX
AREA
D
E
e
9.80
3.80
1.27 BSC
5.80
1
2
H
h
0.2440
0.0195
0.0500
6.20
0.50
1.27
0.25
h x 45°
L
0.41
D
A
L
A1
C
B
e
Ordering Information
Part/Order Number
Marking
Package
Temperature Minimum
Quantities
ICS507M-01
ICS507M-01T
ICS507M-01
ICS507M-01 16 pin SOIC on tape and reel
16 pin narrow SOIC
0 to 70°C
0 to 70°C
-
2500 pieces
ICS507M-01I
ICS507M-01IT
ICS507-01-DSW
ICS507-01-DPK
ICS507-01-DWF
ICS507M-02I
ICS507M-01I
ICS507M-01I 16 pin SOIC on tape and reel
16 pin narrow SOIC
-40 to 85°C 2500 pieces
Probed wafers, cut, on sticky tape 0 to 70°C 1 wafer
-40 to 85°C
-
-
-
-
Tested die in waffle pack
Die on uncut, probed wafers
16 pin narrow SOIC
0 to 70°C
0 to 70°C
-40 to 85°C
1000 pieces
1 wafer
ICS507M-02I
-
ICS507M-02IT
ICS507M-02I 16 pin SOIC on tape and reel
-40 to 85°C 2500 pieces
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 507 C
5
Revision 042600
Printed 11/13/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA •95126• (408)295-9800tel • www.icst.com
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