ICS525-03 [ICSI]

PECL Input OSCaR-TM USER Configurable Clock; PECL输入奥斯卡TM用户可配置的时钟


型号：	ICS525-03
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	PECL Input OSCaR-TM USER Configurable Clock PECL输入奥斯卡TM用户可配置的时钟时钟
文件：	总7页 (文件大小：143K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

ICS525-03

PECL Input OSCaR™ User Configurable Clock

Description

Features

The ICS525-03 are the most flexible way to generate a

high-quality, high-accuracy, high-frequency clock

output from a PECL input. The name OSCaR stands

for OSCillator Replacement, as they are designed to

replace crystal oscillators in almost any electronic

system. The user can configure the device to produce

nearly any output frequency from any input frequency

by grounding or floating the select pins. Neither

microcontroller, software, nor device programmer are

needed to set the frequency. Using Phase-Locked

Loop (PLL) techniques, the device accepts a PECL

clock to produce output clocks up to 250 MHz, keeping

them frequency locked together. Resistors are for

PECL outputs only.

• Packaged as 28-pin SSOP (150 mil body)

• Highly accurate frequency generation

• User determines the output frequency by setting all

internal dividers

• Eliminates need for custom oscillators

• No software needed

• Pull-ups on all select inputs

• PECL input clock frequency of 0.5 to 250 MHz

• Output clock frequencies up to 250 MHz

• Very low jitter

• Operating voltage of 3.0 V or 5.5 V

• 25 mA drive capability at TTL levels

• Ideal for oscillator replacement

• Industrial temperature

For simple multipliers to produce common frequencies,

refer to the LOCO family of parts, which are smaller

• Available in Pb (lead) free package

• Advanced, low-power CMOS process

and more cost effective.

This product is intended for clock generation. It has low

output jitter (variation in the output period), but input to

output skew and jitter are not defined nor guaranteed.

Block Diagram

VDD

62 Ohm

CLK1

Phase Comparator,

Charge Pump, and

Loop Filter

270 Ohm

Output

Divider

Reference

Divider

PECLIN

VCO

VDD

VCO

Divider

62 Ohm

CLK2

270 Ohm

S2:S0

RES

R6:R0

V8:V0

GND

MDS 525-03 H

Revision 010906

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS525-03

PECL Input OSCaR™ User Configurable Clock

RES Value Table

RES

Pin Assignment

CLK1 CLK2 Pre-divide (P)

CMOS CMOS

1.1 kΩ Resistor PECL PECL

to VDD

VDD

PECL

PECLIN

GND

VDD

CLK2

CLK1

GND

RES

28-pin SSOP

Output Divider and Maximum Output Frequency Table

S0 S1 S2 CLK Max. Output Frequency (MHz)

pin 5 pin 4 pin 3 Output Divider

(OD)

VDD = 5 V

VDD = 3.3 V

RES = 0 RES = 1.1 kΩ RES = 0

RES = 1.1 kΩ

200

100

120

125

100

250

133

200

Note: 0 = connect directly to ground; 1 = connect directly to VDD.

MDS 525-03 H

Revision 010906

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS525-03

PECL Input OSCaR™ User Configurable Clock

Pin Descriptions

Number

Name

Type

Pin Description

1, 2,

24-28

R5, R6,

R0-R4

I(PU)

Reference divider word input pins determined by user. Forms a binary

number from 0 to 127.

3, 4, 5

6, 23

S0, S1, S2

VDD

I(PU)

Select pins for output divider determined by user. See table above.

Power Connect to VDD.

PECLIN

GND

Input

PECL input.

Complementary PECL input.

9, 20

10 - 18

Power Connect to ground.

V0 - V8

I(PU)

VCO divider word input pins determined by user. Forms a binary number from

0 to 511.

RES

CLK1

CLK2

Input

Select eithe PECL or CMOS outputs. See table above.

Output Output clock. Either PECL or CMOS determined by RES.

KEY: I(PU) = Input with internal pull-up resistor.

Output Clock Selection

If RES is connected directly to ground, CLK1 and CLK2 are low skew, CMOS outputs clocks. They are not

complementary. If RES is connected to VDD through a 1.1 kΩ resistor, then CLK1 and CLK2 become

complementary PECL outputs which require the external resistor network shown in the the block diagram. Refer to

Application Note MAN09 for additional information.

MDS 525-03 H

Revision 010906

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS525-03

PECL Input OSCaR™ User Configurable Clock

Also, the following operating ranges should be

observed:

External Components/Crystal

Selection

(VDW+8)

(RDW+2)

<350 MHz at 5.0 V or

<250 MHz at 3.3 V

10 MHz < Input frequency x P x

Decoupling Capacitors

The ICS525-03 requries two 0.01µF decoupling

capacitors to be connected between VDD and GND,

one on each side of the chip. The capacitor must be

connected close to the device to minimize lead

inductance. No external power supply filtering is

required for this device.

Input Frequency

200 kHz <

(RDW+2)

(See table on page 2 for full details of maximum output)

The dividers are expressed as integers, so that if a

66.66 MHz PECL output is desired from a 14.31818

PECL input, the Reference Divider Word (RDW) should

be 59 and the VCO Divider Word (VDW) should be

276, with an Output Divider (OD) of 1. To select PECL

outputs, the RES pin should be tied to VDD with a

1.1kΩ resistor.

External Resistors

If PECL outputs are desired, RES should be tied to

VDD with a 1.1 kΩ resistor. Each output needs a

resistive network of 62Ω and 270Ω per the block

diagram on page 1. Application note MAN09 gives

more information about resistor selection.

In this example, R6:R0 is 100010100, and S2:S0 is

110. Since all of these inputs have pull-up reistors, it is

only necessary to ground the zero pins, namely V7, V6,

V5, V3, V1, V0, R6, R2 and S0.

Determining (setting) the Output Frequency

Users have full control in setting the desired output

frequency over the range shown in the table on page 2.

To replace a standard oscillator, users should connect

the divider select input pins directly to ground (or VDD,

although this is not required because of internal

pull-ups) during Printed Circuit Board layout. The

ICS525-03 will automatically produce the correct clock

when all components are soldered. It is also possible to

connect the inputs to parallel I/O ports to switch

frequencies. By choosing divides carefully, the number

of inputs which need to be changed can be minimized.

Observe the restrictions on allowed values of VDW and

RDW.

To determine the best combination of VCO, reference,

and output divide, use the ICS525 Calculator on our

web site:

www.icst.com/products/ics525inputForm.html. The

online form is easy to use and quickly shows you up to

three options for these settings. Alternately, you may

send an e-mail to ics-mk@icst.com.

The output of the ICS525-03 can be determined by the

following simple equation:

(VDW + 8)

--------------------------------------------

CLK Frequency = Input Frequency × Px

(RDW + 2) • OD

Where:

Reference Divider Word (RDW) = 0 to 127

VCO Divider Word (VDW) = 0 to 511

Output Divider (OD) = values on page 2

Pre-divide (P) = values on page 2 under RES Value

Table

MDS 525-03 H

Revision 010906

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS525-03

PECL Input OSCaR™ User Configurable Clock

Absolute Maximum Ratings

Stresses above the ratings listed below can cause permanent damage to the ICS525-03. These ratings,

which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of

the device at these or any other conditions above those indicated in the operational sections of the

specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can

affect product reliability. Electrical parameters are guaranteed only over the recommended operating

temperature range.

Item

Rating

Supply Voltage, VDD

All Inputs and Outputs

7 V

-0.5 V to VDD+0.5 V

-40 to +85°C

Ambient Operating Temperature, Industrial

Storage Temperature

-65°C to 150°C

125°C

Junction Temperature

Soldering Temperature

260°C (max. of 10 seconds)

DC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V

Parameter

Operating Voltage

Symbol

VDD

Conditions

Min.

Typ.

Max.

Units

3.0

5.5

Operating Supply Current

IDD

60 MHz out, no load

Operating Supply Current,

LVPECL mode

IDD

With termination

resistors

Input High Voltage

Input Low Voltage

0.8

Peak-to-peak Input Voltage

Common Mode Range

Output High Voltage

PECLIN, PECLIN

0.3

VDD-1.4

2.4

VDD-0.6

= -25 mA, CMOS

= 25 mA, CMOS

out

Output Low Voltage

0.4

out

Short Circuit Current

Input Capacitance

CMOS out

V, R, S select pins

On-chip Pull-up Resistor

270

kΩ

MDS 525-03 H

Revision 010906

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS525-03

PECL Input OSCaR™ User Configurable Clock

AC Electrical Characteristics

Unless stated otherwise, VDD = 3.3 V

Parameter

Symbol

Conditions

Min. Typ. Max. Units

Input Frequency

Clock input

0.5

250

MHz

Output Frequency, VDD=4.5 to

5 V

OD = 1

250

MHz

OUT

Output Frequency, VDD=3.0 to

3.6 V

OD = 1

200

MHz

Output Clock Rise Time, CMOS

clock

0.8 to 2.0 V

2.0 to 0.8 V

at VDD/2

Output Clock Fall Time, CMOS

clock

Output Clock Duty Cycle, even

output dividers

Output Clock Duty Cycle, odd

output dividers

Absolute Clock Period Jitter

One Sigma Clock Period Jitter

Deviation from mean

One Sigma

350

125

MDS 525-03 H

Revision 010906

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS525-03

PECL Input OSCaR™ User Configurable Clock

Package Outline and Package Dimensions (28-pin SSOP, 150 mil Body)

Package dimensions are kept current with JEDEC Publication No. 95, MO-153

Millimeters

Inches

Min

Symbol

Min

Max

1.75

0.25

1.50

0.30

0.25

10.00

6.20

4.00

Max

.069

.010

.059

.012

.010

.394

.244

.157

1.35

0.10

.053

.0040

.008

.007

.386

.228

.150

INDEX

AREA

0.20

0.18

9.80

5.80

3.80

1 2

0.635 Basic

0.025 Basic

0.40

0°

1.27

.016

.050

8°

0°

aaa

0.10

0.004

- C -

SEATING

PLANE

aaa C

Ordering Information

Part / Order Number

ICS525R-03I

Marking

ICS525R-03I

Shipping Packaging

Tubes

Package

Temperature

-40 to +85°C

28-pin SSOP

ICS525R-03IT

ICS525R-03I

ICS525R-03ILF

Tape and Reel

Tubes

ICS525R-03ILF

ICS525R-03ILFT

Tape and Reel

Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)

assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would

result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial

applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary

environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any

circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or

critical medical instruments

MDS 525-03 H

Revision 010906

Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com

ICS525-03 [ICSI]

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