ICS525-04 [ICSI]
OSCaR-TM User Configurable PECL Clock; 奥斯卡TM用户可配置的时钟PECL
| 型号： | ICS525-04 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | OSCaR-TM User Configurable PECL Clock |
| 文件： | 总7页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS525-04
TM
OSCaR User Configurable PECL Clock
Description
Features
TM
The ICS525-04 OSCaR is the most flexible way to
generate a high quality, high frequency differential
PECL clock output from a crystal or CMOS clock input.
• Packaged as 28 pin SSOP (150 mil body)
• Highly accurate frequency generation
• User determines the output frequency by setting all
TM
The name OSCaR stands for Oscillator
internal dividers
Replacement, as it is designed to replace crystal
oscillators in almost any electronic system. Users can
easily configure the device to produce nearly any
output frequency from any input frequency by
grounding or floating the select pins. Neither
microcontroller, software, nor device programmer are
needed to set the frequency. Using Phase Locked Loop
techniques, the device accepts a crystal or clock to
produce output clocks up to 156 MHz at 3.3V, keeping
them frequency locked together.
• Eliminates need for custom oscillators
• No software needed
• Pull-ups on select inputs
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 2 - 50 MHz
• Output clock frequencies up to 156 MHz at 3.3V
• Output clock frequencies up to 200 MHz at 5V
• Very low jitter
• PECL levels set by external resistors
• Operating voltage of 3.3V or 5V
• Ideal for oscillator replacement
• Industrial temperature version available
• Advanced, low power CMOS process
For simple multipliers to produce common frequencies,
TM
refer to the LOCO family of parts, which are smaller
and more cost effective.
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input to
output skew and jitter are not defined nor guaranteed.
For applications which require defined input to output
timing, use the ICS527-02.
Block Diagram
560Ω
2
VDD
RES
VDD
VDD
82Ω
X1/ICLK
PECL
PECL
Phase Comparator,
Charge Pump, and
Loop Filter
Reference
Divider
Crystal
Oscillator
VCO
820Ω
Crystal or
clock input
Output
Divider
GND
X2
VDD
82Ω
VCO
Divider
Optional crystal capacitors
820Ω
GND
7
9
2
3
GND
R6:R0
V8:V0
S2:S0
MDS 525-04 B
1
Revision 091802
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS525-04
OSCaR User Configurable PECL Clock
TM
Pin Assignment
R5
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R4
R6
2
R3
S0
3
R2
S1
4
R1
S2
5
R0
VDD
X1/ICLK
X2
6
VDD
PECL
PECL
GND
RES
V8
7
8
GND
V0
9
10
11
12
13
14
V1
V2
V7
V3
V6
V4
V5
28 pin 150 mil body SSOP
Maximum Output Frequency and Output Divider Table
S2
S1
S0 CLKOutput
Max Output Frequency (MHz)
VDD = 5V VDD = 3.3V
Pin 5 Pin 4 Pin 3
Divider
0 - 70 °C
-40 - 85 °C
0 - 70 °C
-40 - 85 °C
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6
2
8
4
5
7
1
3
45
120
34
44
117
33
27
81
20
40
32
23
162
54
26
77
19
38
31
22
154
51
68
66
54
53
39
38
200
90
195
89
MDS 525-04 B
2
Revision 091802
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS525-04
OSCaR User Configurable PECL Clock
TM
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
R5
R6
Input
Input
Reference divider word input pins determined by user. Forms a binary number from 0
to 127. Internal pull-up.
Reference divider word input pins determined by user. Forms a binary number from 0
to 127. Internal pull-up.
3
S0
S1
Input
Input
Input
Power
Input
Input
Power
Input
Select pins for output divider determined by user. See table above. Internal pull-up.
Select pins for output divider determined by user. See table above. Internal pull-up.
Select pins for output divider determined by user. See table above. Internal pull-up.
Connect to VDD.
4
5
S2
6
VDD
X1/ICLK
X2
7
Crystal connection. Connect to a parallel resonant crystal or input clock.
Crystal connection. Connect to a crystal or leave unconnected for clock.
Connect to ground.
8
9
GND
V0 - V8
10 - 18
VCO divider word input pins determined by user. Forms a binary number from 0 to
511. Internal pull-up.
19
20
21
22
23
24
RES
GND
PECL
PECL
VDD
R0
Input
Power
Output
Output
Power
Input
Bias resistor input. Connect a resistor between this pin and VDD.
Connect to ground.
Complementary PECL output. Connect resistor load to this pin.
PECL output. Connect resistor load to this pin.
Connect to VDD.
Reference divider word input pins determined by user. Forms a binary number from 0
to 127. Internal pull-up.
25
26
27
28
R1
R2
R3
R4
Input
Input
Input
Input
Reference divider word input pins determined by user. Forms a binary number from 0
to 127. Internal pull-up.
Reference divider word input pins determined by user. Forms a binary number from 0
to 127. Internal pull-up.
Reference divider word input pins determined by user. Forms a binary number from 0
to 127. Internal pull-up.
Reference divider word input pins determined by user. Forms a binary number from 0
to 127. Internal pull-up.
MDS 525-04 B
3
Revision 091802
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS525-04
TM
OSCaR User Configurable PECL Clock
Observe the restrictions on allowed values of VDW and
RDW.
External Components
Decoupling Capacitors
The output of the ICS525-04 can be determined by the
following simple equation:
As with any high performance mixed-signal IC, the
ICS525-04 must be isolated from system power supply
noise to perform optimally.
VDW + 8
(RDW + 2) • OD
--------------------------------------------
PECL Frequency = Input Frequency ×
Decoupling capacitors of 0.01µF must be connected
between each VDD and the GND, one on each side of
the chip.The capacitor must be connected close to the
device to minimize lead inductance. No external power
supply filtering is required for this device.
Where:
Reference Divider Word (RDW) = 0 to 127
VCO Divider Word (VDW) = 0 to 511
Output Divider (OD) = values on page 2
External Resistors
A 560Ω resistor must be connected between RES (pin
19) and VDD. A total of four resistors are needed for the
PECL outputs as shown on the block diagram on page
1. The value of these resistors are shown, but can be
varied to change the differential pair output swing and
the common mode voltage. Consult application note
MAN09 for more information.
Also, the following operating ranges should be
observed:
VDW + 8
10M < Input Frequencyx-(--R-----D-----W-------+-----2----) < 2 00 M (5 V )or162M(3.3v))
InputFrequency
Crystal Load Capacitors
200kHz < -----------------------------------------------
(RDW + 2)
The total on-chip capacitance for a crystal is
approximately 16 pF, so a parallel resonant,
See table on page 2 for full details of maximum
output.
fundamental mode crystal with this value of load
(correlation) capacitance should be used. For crystals
with a specified load capacitance greater than 16 pF,
crystal capacitors may be connected from each of the
pins X1 and X2 to Ground as shown in the block
diagram. The value (in pF) of these crystal caps should
be (CL - 16)*2, where CL is the crystal load
capacitance. These external capacitors are only
required for applications where the exact frequency is
critical. For a clock input, connect to X1 and leave X2
unconnected (no capacitors on either).
The dividers are expressed as integers. For example, if
a 66.66 MHz output on CLK1 is desired from a
14.31818 MHz input, the VCO divider word (VDW)
should be 276, with an output divide (OD) of 2. In this
example, R6:R0 is 0111011, V8:V0 is 100010100 and
S2:S0 is 001. Since all of these inputs have pull-up
resistors, it is only necessary to ground the zero pins,
namely V7, V6, V5, V3, V1, V0, R6, R2, S2, and S1.
To determine the best combination of VCO, reference,
and output divide, use the ICS525 Calculator on our
web site: www.icst.com. The online form is easy to use
and quickly shows you up to three options for these
settings. Alternately, you may send an e-mail to
ics-mk@icst.com.
Determining the Output Frequency
Users have full control in setting the desired output
frequency over the range shown in the table on page 2.
To replace a standard oscillator, users should connect
the divider select input pins directly to ground (or VDD,
although this is not required because of internal
pull-ups) during Printed Circuit Board layout. The
ICS525-04 will automatically produce the correct clock
when all components are soldered. It is also possible to
connect the inputs to parallel I/O ports to switch
frequencies. By choosing divides carefully, the number
of inputs which need to be changed can be minimized.
MDS 525-04 B
4
Revision 091802
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS525-04
OSCaR User Configurable PECL Clock
TM
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS525-04. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7V
-0.5V to VDD+0.5V
-40 to +85°C
-65 to +150°C
175°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature, ICS525R-04
Ambient Operating Temperature, ICS525R-04I
Power Supply Voltage (measured in respect to GND)
0
-40
+3.0
+85
°C
+5.5
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 10%, Ambient Temperature 0 to +70°C
Parameter
Operating Voltage
Supply Current
Symbol
VDD
Conditions
Min.
Typ.
Max. Units
3.0
5.5
V
IDD
15 MHz in, 60MHz out,
no load
34
60
mA
15MHz in, 60MHz out,
VDD = 5V
mA
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
V
2
V
V
V
V
V
IH
V
0.8
IL
VDD/2+1
2.4
V
X1/ICLK only
X1/ICLK only
VDD/2
VDD/2
IH
VDD/2-1
V
IL
V
I
= -12 mA
OH
OH
MDS 525-04 B
5
Revision 091802
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS525-04
OSCaR User Configurable PECL Clock
TM
Parameter
Output Low Voltage
Input Capacitance
Symbol
Conditions
Min.
Typ.
Max. Units
V
I
= 12 mA
0.4
V
OL
OL
C
V, R, S select pins
V, R, S select pins
5
pF
kΩ
IN
On-chip pull-up resistor
R
270
PU
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V 5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Crystal input
5
2
1
1
1
1
27
50
MHz
MHz
MHz
MHz
MHz
MHz
ps
Input Frequency
F
IN
Clock input
0 to +70°C
120
117
81
Output Frequency with OD=2,
VDD=4.5 to 5
F
F
OUT
OUT
-40 to +85°C
0 to +70°C
Output Frequency with OD=2,
VDD=3.0 to 3.3
-40 to +85°C
Deviation from mean
77
Absolute Clock Period Jitter
One sigma Clock Period Jitter
t
50
20
ja
t
ps
js
MDS 525-04 B
6
Revision 091802
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
ICS525-04
TM
OSCaR User Configurable PECL Clock
Package Outline and Package Dimensions (28 pin SSOP, 150 mil Body, 0.025 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters
Inches
Min
28
Symbol
Min
Max
1.75
0.25
1.50
0.30
0.25
10.00
6.20
4.00
Max
.069
.010
.059
.012
.010
.394
.244
.157
A
A1
A2
b
1.35
0.10
--
0.20
0.18
9.80
5.80
3.80
.053
.0040
--
.008
.007
.386
.228
.150
E1
E
INDEX
AREA
C
D
E
1
2
E1
e
L
0.635 Basic
0.025 Basic
D
0.40
0°
1.27
.016
.050
8°
α
8°
0°
aaa
--
0.10
--
0.004
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Shipping
packaging
Part / Order Number
Marking
Package
Temperature
ICS525R-04
ICS525R-04T
ICS525R-04I
ICS525R-04IT
ICS525R-04
ICS525R-04
ICS525R-04I
ICS525R-04I
Tubes
28 pin SSOP
28 pin SSOP
28 pin SSOP
28 pin SSOP
0 to +70°C
0 to +70°C
Tape and Reel
Tubes
-40 to +85°C
-40 to +85°C
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments
MDS 525-04 B
7
Revision 091802
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 295-9800 ● www.icst.com
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