ICS525-12 [ICSI]
User Configurable Clock; 用户可配置的时钟
| 型号： | ICS525-12 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | User Configurable Clock |
| 文件： | 总9页 (文件大小：179K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS525-01/02/11/12
User Configurable Clock
Description
Features
The ICS525-01/02/11/12 are the most flexible way to
generate a high-quality, high-accuracy, high-frequency
clock output from an inexpensive crystal or clock input.
The user can configure the device to produce nearly
any output frequency from any input frequency by
grounding or floating the select pins. Neither
microcontroller, software, nor device programmer are
needed to set the frequency. Using Phase-Locked
Loop (PLL) techniques, the device accepts a standard
fundamental mode, inexpensive crystal to produce
output clocks up to 250 MHz. It can also produce a
highly accurate output clock from a given input clock,
keeping them frequency locked together.
• Packaged as 28-pin SSOP (150 mil body)
• Industrial and commercial versions available in Pb
(lead) free package
• User determines the output frequency by setting all
internal dividers
• Eliminates need for custom oscillators
• No software needed
• Online calculator determines register settings
• Pull-ups on all select inputs
• Input crystal frequency of 5 - 27 MHz
• Input clock frequency of 2 - 50 MHz
• Very low jitter
• Duty cycle of 45/55 up to 200 MHz
• Operating voltage of 3.0 V or 5.5 V
• Ideal for oscillator replacement
• Industrial temperature version available
• For Zero Delay, refer to the ICS527
For similar capability with a serial interface, use the
ICS307. For simple multipliers to produce common
frequencies, refer to the ICS50x family of parts, which
are smaller and more cost effective.
These products are intended for clock generation. They
have low output jitter (variation in the output period), but
input to output skew and jitter are not defined nor
guaranteed. For applications which require defined
input to output timing, use the ICS527-01.
Block Diagram
2
VDD
PD
X1/ICLK
CLK
REF
Phase Comparator,
Charge Pump, and
Loop Filter
Reference
Divider
Crystal
Oscillator
VCO
Crystal or clock
input
Output
Divider
X2
VCO
Divider
Optional crystal capacitors
2
7
9
3
GND
R6:R0
V8:V0
S2:S0
MDS 525-01/02/11/12 Q
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Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS525-01/02/11/12
User Configurable Clock
Pin Assignment
R5
R6
1
28
27
26
25
24
23
22
21
20
19
18
17
16
15
R4
2
R3
S0
3
R2
S1
4
R1
S2
5
R0
VDD
X1/ICLK
X2
6
VDD
REF
CLK
GND
PD
V8
7
8
GND
V0
9
10
11
12
13
14
V1
V2
V7
V3
V6
V4
V5
ICS525-01/-02/-11/-12
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1, 2,
24-28
R5, R6,
R0-R4
I(PU)
Reference divider word input pins determined by user. Forms a binary number from 0
to 127.
3, 4, 5
6, 23
7
S0, S1, S2
VDD
I(PU)
Power
X1
Select pins for output divider determined by user. See table on page 3
Connect to VDD.
X1/ICLK
X2
Crystal connection. Connect to a parallel resonant fundamental crystal or input clock.
Crystal connection. Connect to a crystal or leave unconnected for clock.
Connect to ground.
8
X2
9, 20
10 - 18
GND
Power
I(PU)
V0 - V8
VCO divider word input pins determined by user. Forms a binary number from 0 to
511.
19
21
22
PD
Input
Output
Output
Power-down. Active low. Turns off entire chip when low. Clock outputs stop low.
Output clock determined by status of R0-R6, V-V8, S0-S2, and input frequency.
Reference output. Buffered crystal oscillator (or clock ) output.
CLK
REF
KEY: I(PU) = Input with internal pull-up resistor; X1, X2 = crystal connections
MDS 525-01/02/11/12 Q
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Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS525-01/02/11/12
User Configurable Clock
ICS525-01 Output Frequency and Output Divider Table
S2
S1
S0 CLKOutput
Output Frequency Range (MHz)
VDD = 5 V VDD = 3.3 V
Pin 5 Pin 4 Pin 3
Divider
0 - 70°C
-40 to +85°C
3–23
0 - 70°C
-40 to +85°C
3–16
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
2
3–26
15–160
3.75–40
7.5–80
6–50
3–18
15–100
3.75–25
7.5–50
6–34
15–140
3.75–36
7.5–72
6–45
15–90
3.75–22
7.5–45
6–30
8
4
5
7
4–40
4–36
4–26
4–23
9
3.3–33.3
5–53
3.3–30
5–47
3.3–20
5–27
3.3–18
5–24
6
ICS525-02 Output Frequency and Output Divider Table
Output Frequency Range (MHz)
S2
S1
S0 CLKOutput
Pin 5 Pin 4 Pin 3
Divider
VDD = 5 V
-40 to +85°C
5–67
VDD = 3.3 V
-40 to +85°C
5–40
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6
2
8
4
5
7
1
3
15–200
3.75–50
7.5–100
6–80
15–120
3.75–30
7.5–60
6–48
4–57
4–34
30–250
10–133
30–200
10–80
ICS525-11 Output Frequency and Output Divider Table
Output Frequency Range (MHz)
VDD = 5 V VDD = 3.3 V
S2
S1
S0 CLKOutput
Pin 5 Pin 4 Pin 3
Divider
0 - 70°C
-40 to +85°C
0.75–5.75
3.75–35
0 - 70°C
-40 to +85°C
0.75–4
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
10
2
0.75–6.5
3.75–40
0.94–10
1.875–20
1.5–12.5
1–10
0.75–4.5
3.75–25
3.75–22.5
0.94–5.5
8
0.94–9
0.94–6.25
4
1.875–18
1.5–11.25
1–9
1.875–12.5 1.875–11.25
5
1.5–8.5
1–6.5
1.5–7.5
1–5.75
7
9
0.83–8.33
1.25–13.25
0.83–7.5
1.25–11.75
0.83–5
0.83–4.5
1.25–6
6
1.25–6.75
MDS 525-01/02/11/12 Q
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Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS525-01/02/11/12
User Configurable Clock
ICS525-12 Output Frequency and Output Divider Table
S2
S1
S0 CLKOutput
Output Frequency Range (MHz)
Pin 5 Pin 4 Pin 3
Divider
VDD = 5 V
-40 to +85°C
1.25–16.75
3.75–50
VDD = 3.3 V
-40 to +85°C
1.25–10
3.75–30
0.94–7.5
1.875–15
1.5–12
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
6
2
8
4
5
7
1
3
0.94–12.5
1.875–25
1.5–20
1–14.25
1–8.5
7.5–62.5
7.5–50
2.5–33.25
2.5–20
MDS 525-01/02/11/12 Q
4
Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS525-01/02/11/12
User Configurable Clock
(VDW + 8)
--------------------------------------------
CLK Frequency = Input Frequency × 2x
External Components/Crystal
Selection
(RDW + 2) • OD
Where:
Decoupling Capacitors
Reference Divider Word (RDW) = 0 to 127 (0 not
permitted for ICS525-01/-11)
The ICS525-01/02/11/12 requries two 0.01µF
decoupling capacitors to be connected between VDD
and GND, one on each side of the chip. The capacitor
must be connected close to the device to minimize lead
inductance.
VCO Divider Word (VDW) = 0 to 511 (0, 1, 2, 3 not
permitted for ICS525-01/-11)
Output Divider (OD) = values on pages 3-4
Also, the following operating ranges should be
observed:
External Resistors
A 33Ω series termination resistor should be used on
the CLK and REF pins.
1. The output frequency must be in the ranges listed on
pages 3-4.
Crystal Load Capacitors
2. The phase detector frequency must be above 200
kHz.
The approximate total on-chip capacitance for a crystal
is 16 pF, so a parallel resonant, fundamental mode
crystal with this value of load (correlation) capacitance
should be used. For crystals with a specified load
capacitance greater than 16 pF, crystal capacitors may
be connected from each of the pins X1 and X2 to
Ground as shown in the block diagram. The value (in
pF) of these crystal caps should be (CL -16)*2, where
CL is the crystal load capacitance in pF. These external
capacitors are only required for applications where the
exact frequency is critical. For a clock input, connect to
X1 and leave X2 unconnected (no capacitors on
either).
InputFrequency
200kHz < -----------------------------------------------
(RDW + 2)
Since all of the inputs have pull-up resistors, it is only
necessary to ground the pins that need to be set to
zero.
Which Part to Use?
The ICS525-01 is the original configurable clock.
The ICS525-02 has a higher maximum output
grequency and a slightly different set of output dividers.
The ICS525-11 has the same divider set as the -01 but
is optimized for low frequency operation.
Determining the Output Frequency
Users have full control in setting the desired output
frequency over the range shown in the tables on pages
3-4. To replace a standard oscillator, users should
connect the divider select input pins directly to ground
(or VDD, although this is not required because of
internal pull-ups) during Printed Circuit Board layout.
The ICS525 will automatically produce the correct
frequency when all components are soldered. It is also
possible to connect the inputs to parallel I/O ports to
switch frequencies. By choosing divides carefully, the
number of inputs which need to be changed can be
minimized. Observe the restrictions on allowed values
of VDW and RDW.
The ICS525-12 has the same divider set as the -02 but
is optimized for low frequency operation.
To determine the best combination of VCO, reference,
and output divide, use the ICS525 Calculator on our
web site.
Configuration Pin Settings
The output of the ICS525 can be determined by the
following simple equation:
MDS 525-01/02/11/12 Q
5
Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS525-01/02/11/12
User Configurable Clock
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS525-01/02/11/12. These
ratings, which are standard values for ICS commercially rated parts, are stress ratings only. Functional
operation of the device at these or any other conditions above those indicated in the operational sections
of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
can affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70°C
Ambient Operating Temperature, Commercial
Ambient Operating Temperature, Industrial
Storage Temperature
-40 to +85°C
-65°C to 150°C
125°C
Junction Temperature
Soldering Temperature
260°C (max. of 10 seconds)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V
Parameter
Operating Voltage
Symbol
VDD
Conditions
Min.
Typ.
Max. Units
3.0
5.5
V
Operating Supply Current
IDD
60 MHz out, no load,
15 MHz crystal,
8
mA
ICS525-01/02 only
Operating Supply Current
IDD
IDD
40 MHz out, 15 MHz
crystal, ICS525-11/12
only
6
4
mA
µA
Operating Supply Current,
Power-down
Pin 19 = 0, Note 1
Input High Voltage
Input Low Voltage
V
2
V
V
V
IH
V
0.8
VDD/2-1
0.4
IL
VDD/2+1
Input High Voltage,
X1/ICLK only
V
ICLK (pin7)
ICLK (pin7)
VDD/2
VDD/2
IH
Input Low Voltage, X1/ICLK
only
V
V
IL
VDD-0.4
Output High Voltage
Output Low Voltage
V
I
I
= -12 mA
= 12 mA
V
V
OH
OH
V
OL
OL
MDS 525-01/02/11/12 Q
6
Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS525-01/02/11/12
User Configurable Clock
Parameter
Short Circuit Current
Input Capacitance
Symbol
Conditions
Min.
Typ.
Max. Units
CLK and REF outputs
V, R, S pins and pin 19
V, R, S pins and pin 19
55
4
mA
pF
C
IN
On-chip Pull-up Resistor
R
270
kΩ
PU
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Crystal input
5
2
27
50
MHz
MHz
ns
Input Frequency
F
IN
Clock input
0.8 to 2.0 V
2.0 to 0.8 V
Output Clock Rise Time
Output Clock Fall Time
1
1
ns
Output Clock Duty Cycle, OD =
2, 4, 6, 8, or 10
49 to
51
At VDD/2
At VDD/2
At VDD/2
45
40
35
55
60
65
50
10
%
%
Output Clock Duty Cycle, OD =
3, 5, 7, or 9
Output Clock Duty Cycle, OD =
1 (-02 and -12 only)
Power-down Time, PD low to
clocks stopped
ns
ms
ps
ps
ps
ps
ps
ps
ps
ps
Power-up Time, PD high to
clocks stable
Absolute Clock Period Jitter,
ICS525-01, Note 2
t
Deviation from mean
One Sigma
140
45
ja
One Sigma Clock Period Jitter,
ICS525-01, Note 2
t
js
ja
Absolute Clock Period Jitter,
ICS525-02, Note 2
t
Deviation from mean
One Sigma
85
One Sigma Clock Period Jitter,
ICS525-02, Note 2
t
30
js
ja
Absolute Clock Period Jitter,
ICS525-11, Note 2
t
Deviation from mean
One Sigma
160
40
One Sigma Clock Period Jitter,
ICS525-11, Note 2
t
js
ja
Absolute Clock Period Jitter,
ICS525-12, Note 2
t
Deviation from mean
One Sigma
160
40
One Sigma Clock Period Jitter,
ICS525-12, Note 2
t
js
MDS 525-01/02/11/12 Q
7
Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS525-01/02/11/12
User Configurable Clock
NOTE 1: Phase relationship between input and output can change at power-up. For a fixed phase
relationship, see the ICS527.
NOTE 2: For 16 MHz, 100 MHz output. Use the -02 for lowest jitter.
Package Outline and Package Dimensions (28-pin SSOP, 150 mil Body)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters
Inches*
Min
28
Symbol
Min
1.35
0.10
--
Max
1.75
0.25
1.50
0.30
0.25
10.00
6.20
4.00
Max
.069
.010
.059
.012
.010
.394
.244
.157
A
A1
A2
b
.053
.0040
--
.008
.007
.386
.228
.150
E1
E
0.20
0.18
9.80
5.80
3.80
INDEX
AREA
C
D
E
E1
e
1 2
0.635 Basic
0.025 Basic
L
0.40
0°
1.27
.016
.050
8°
D
α
8°
0°
aaa
--
0.10
--
0.004
*For reference only. Controlling dimensions in mm.
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
aaa C
MDS 525-01/02/11/12 Q
8
Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS525-01/02/11/12
User Configurable Clock
Ordering Information
Part / Order Number
ICS525-01R
Marking
ICS525-01R
ICS525-01R
Shipping Packaging
Tubes
Package
Temperature
0 to +70°C
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
28-pin SSOP
ICS525-01RT
Tape and Reel
Tubes
0 to +70°C
ICS525-01RLF
ICS525-01RLFT
ICS525-01RI
ICS525-01RLF
ICS525-01RLF
ICS525-01RI
ICS525-01RI
ICS525-01RILF
ICS525-01RILF
ICS525R-02I
ICS525R-02I
ICS525R-02ILF
ICS525R-02ILF
ICS525R-11
0 to +70°C
Tape and Reel
Tubes
0 to +70°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
0 to +70°C
ICS525-01RIT
ICS525-01RILF
ICS525-01RILFT
ICS525R-02I
Tape and Reel
Tubes
Tape and Reel
Tubes
ICS525R-02IT
ICS525R-02ILF
ICS525R-02ILFT
ICS525R-11
Tape and Reel
Tubes
Tape and Reel
Tubes
ICS525R-11T
ICS525R-11LF
ICS525R-11LFT
ICS525RI-11
ICS525R-11
Tape and Reel
Tubes
0 to +70°C
ICS525R-11LF
ICS525R-11LF
ICS525RI-11
ICS525RI-11
ICS525RI-11LF
ICS525RI-11LF
ICS525RI-12
ICS525RI-12
ICS525RI-12LF
ICS525RI-12LF
0 to +70°C
Tape and Reel
Tubes
0 to +70°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
-40 to +85°C
ICS525RI-11T
ICS525RI-11LF
ICS525RI-11LFT
ICS525RI-12
Tape and Reel
Tubes
Tape and Reel
Tubes
ICS525RI-12T
ICS525RI-12LF
ICS525RI12LFT
Tape and Reel
Tubes
Tape and Reel
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments
MDS 525-01/02/11/12 Q
9
Revision 101105
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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