ICS548M-03T [ICSI]
Low Skew Clock Inverter and Divider; 低偏移的时钟逆变器和分频器
| 型号： | ICS548M-03T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low Skew Clock Inverter and Divider |
| 文件： | 总4页 (文件大小：78K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ADVANCE INFORMATION
ICS548-03
Low Skew Clock Inverter and Divider
Features
Description
• Packaged in 16 pin narrow (150 mil) SOIC
• Input clock up to 160 MHz in the non-PLL mode
• Provides clock outputs of CLK, CLK, and CLK/2
• Low skew (500 ps) on CLK, CLK, and CLK/2
• All outputs can be tri-stated
The ICS548-03 is a low cost, low skew, high
performance general-purpose clock designed to
produce a set of one output clock, one inverted
output clock, and one clock divided-by-2. Using
our patented analog Phase-Locked Loop (PLL)
techniques, the device operates from a frequency
range from 10 MHz to 120 MHz in the PLL mode,
and up to 160 MHz in the non-PLL mode.
• Entire chip can be powered down by changing one
or two select pins
In applications that to need maintain low phase
noise in the clock tree, the non-PLL (when
S3=S2=1) mode should be used.
• 3.3V or 5.0V operating voltage
This chip is not a zero delay buffer. Many
applications may be able to use the ICS527 for zero
delay dividers.
Block Diagram
Output
CLK
Buffer
Clock
4
S3:S0
Synthesis
and
Divider
Circuitry
Output
Buffer
CLK
Input
Buffer
Output
Buffer
Clock Input
CLK/2
OE (All outputs)
MDS 548-03
1
Revision 042700
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
ADVANCE INFORMATION
ICS548-03
Low Skew Clock Inverter and Divider
CLK, CLK, and CLK/2 Select Table (in MHz)
Pin Assignment
S3 S2 S1 S0 CLK, CLK
CLK/2
Low
PLL Input Range
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Low
Input/4
Input
Off Power down
ICLK
VDD
VDD
S3
1
16 DC
15 DC
14 DC
13 CLK
Input/8
Input/2
Input/4
Low
On
On
On
20 -120
20 -120
20 -120
2
3
4
5
6
7
Input/2
Low
Off Power down
Input x 2
Input/5
Input/3
Low
Input
On
On
On
20 - 60
20 -120
20 - 120
Input/10
Input/6
Low
12
11
GND
GND
S2
CLK
CLK/2
Off Power down
10 OE
Input/4
Input
Input/8
Input/2
Input/4
Low
On
On
On
10 - 60
10 - 60
10 - 60
S1
9
S0
8
Input/2
Low
Off Power down
Input/6
Input/8
Input/2
Input/12
Input/16
Input/4
Off
Off
Off
0 - 160
0 - 160
0 - 160
Pin Descriptions
Number
Name
Type
Description
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
ICLK
VDD
VDD
S3
GND
GND
S2
S0
S1
OE
CLK/2
CLK
CLK
DC
DC
DC
CI
P
P
I
P
P
I
I
I
I
O
O
O
-
-
-
Input Clock. Connect to a CMOS level input clock.
Connect to +3.3V or +5.0V.
Connect to +3.3V or +5.0V.
Clock Select Pin 3. See above table.
Connect to ground.
Connect to ground.
Clock Select Pin 2. See above table.
Clock Select Pin 0. See above table.
Clock Select Pin 1. See above table.
Output Enable. Tri-states all clock outputs when low.
Clock Output divided by 2. See above table.
Clock Output. See above table.
Inverted Clock Output. See above table.
Don't Connect. Do not connect anything to this pin.
Don't Connect. Do not connect anything to this pin.
Don't Connect. Do not connect anything to this pin.
Key: I = Input; O = Output; P = Power Supply connection; CI = Clock Input
MDS 548-03
2
Revision 042700
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
ADVANCE INFORMATION
ICS548-03
Low Skew Clock Inverter and Divider
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (stresses beyond these can permanently damage the device)
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
7
VDD+0.5
VDD+0.5
70
V
V
-0.5
-0.5
0
Clock Output
V
Ambient Operating Temperature
Soldering Temperature
Storage temperature
°C
°C
°C
Max of 10 seconds
260
-65
150
DC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Operating Voltage, VDD
3
5.5
(VDD/2)-1
0.8
V
V
Input High Voltage, VIH, ICLK only
Input Low Voltage, VIL, ICLK only
Input High Voltage, VIH
ICLK (Pin 1)
ICLK (Pin 1)
All other inputs
All other inputs
IOH=-8mA
(VDD/2)+1
VDD/2
VDD/2
V
2
V
Input Low Voltage, VIL
V
Output High Voltage, VOH, CMOS level
Output High Voltage, VOH
VDD-0.4
2.4
V
IOH=-12mA
IOL=12mA
V
Output Low Voltage, VOL
0.4
V
IDD Operating Supply Current, 100 MHz clock S3=S2=S0=0, S1=1
TBD
±50
5
mA
mA
pF
Short Circuit Current
Each output
All inputs
Input Capacitance, S3, S2, S1, S0 , and OE
AC CHARACTERISTICS (VDD = 3.3V unless otherwise noted)
Input Frequency, clock input, PLL on
10
0
120
160
120
MH z
MH z
MH z
ns
Input Frequency, clock input, PLL off
Output Frequency (see table on page 2)
Output Clock Rise Time
Mode dependent
0.8 to 2.0V
0
1
1
Output Clock Fall Time
2.0 to 0.8V
ns
Output Clock Duty Cycle
at VDD/2
45
49 to 51
55
50
50
%
Output Enable Time, OE high to output on
Output Disable Time, OE low to tri-state
Absolute Clock Period Jitter, PLL modes
One Sigma Clock Period Jitter, PLL modes
Output clock skew for CLK, CLK, or CLK/2
ns
ns
Deviation from mean
at VDD/2
TBD
TBD
ps
ps
500
ps
Note 1: The phase relationship between input and output clocks can change at power up. Use the ICS570 or ICS527 Zero Delay
Buffers for a guaranteed phase relationship.
External Components/Application Information
The device requires a 0.01 µF decoupling capacitor between pins 3 and 5, as close to the pins as possible.
Connect pin 2 directly to pin 3, and pin 6 directly to pin 5. Series termination resistors of 33 Wcan be used
on all used clock outputs, also close to the device. Leave any unused clock outputs floating. There are no
pull-up resistors on the input pins, so they should be connected directly to VDD or ground.
MDS 548-03
3
Revision 042700
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
ADVANCE INFORMATION
ICS548-03
Low Skew Clock Inverter and Divider
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC publication no. 95.)
16 pin SOIC narrow
Inches
Symbol Min Max
0.059 0.069
0.004 0.0098 0.10
0.013 0.020 0.33
0.007 0.0098 0.19
Millimeters
Min
1.50
Max
1.75
0.25
0.51
0.25
10.00
4.00
A
A1
B
C
D
E
E
H
INDEX
AREA
0.386 0.394
0.150 0.157
.050 BSC
9.80
3.80
e
1.27 BSC
5.80
1
2
H
L
0.228 0.244
6.20
1.27
0.016
0.05
0.41
D
A
A1
C
B
e
L
Ordering Information
Part/Order Number
ICS548M-03
Marking
ICS548M-03
ICS548M-03
Package
16 pin SOIC
16 pin SOIC on tape and reel
Temperature
0 to 70 °C
0 to 70 °C
ICS548M-03T
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 548-03
4
Revision 042700
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
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