ICS557-03 [ICSI]
PCI-EXPRESS CLOCK SOURCE; PCI - Express时钟源
| 型号： | ICS557-03 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | PCI-EXPRESS CLOCK SOURCE |
| 文件： | 总9页 (文件大小：226K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS557-03
PCI-EXPRESS CLOCK SOURCE
Description
Features
The ICS557-03 is a spread spectrum clock generator
supporting PCI-Express and Ethernet requirements.
The device is used for PC or embedded systems to
substantially reduce electromagnetic interference
(EMI). The device provides two differential (HCSL)
spread spectrum outputs. This device is pin configured
to select spread and clock selection. Using ICS’
patented Phase-Locked Loop (PLL) techniques, the
device takes a 25 MHz crystal input and produces two
pairs of differential outputs (HCSL) at 25 MHz, 100
MHz, 125 MHz and 200 MHz clock frequencies. It also
provides spread selection of 0.25%, -0.5%, -0.75%,
and no spread.
• Packaged in 16-pin TSSOP
• Available in Pb (lead) free package
• Supports LVDS Output Levels
• Operating voltage of 3.3 V
• Input frequency of 25 MHz
• Outputs (HCSL, 0.7 V Current mode differential pair)
• Jitter 100 ps (peak-to-peak)
• Spread of 0.25%, -0.5%, -0.75%, and no spread.
• Industrial and commercial temperature ranges
Block Diagram
VDD
2
SS1:SS0
2
CLK0
CLK0
Control
Logic
S1:S0
2
Phase Lock Loop
CLK1
CLK1
X1/ICLK
Clock
Buffer/
25 MHz
Crystal
crystal or clock
Oscillator
X2
2
GND
Optional tuning crystal
capacitors
Rr(IREF)
OE
MDS 557-03 E
1
Revision 061005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-03
PCI-EXPRESS CLOCK SOURCE
Output Select Table 1(MHz)
Pin Assignment
S1
0
S0
0
CLK(1:0), CLK(1:0)
1
VDDXD
CLK0
16
15
14
13
12
11
10
9
S0
25M
100M
125M
200M
0
1
S1
SS0
2
3
4
5
6
7
8
1
0
CLK0
1
1
X1/ICLK
X2
GNDODA
VDDODA
CLK1
Spread Selection Table 2
OE
SS1
SS0
0
Spread %
Center 0.25
Down -0.5
0
0
1
1
GNDXD
SS1
CLK1
IREF
1
0
Down -0.75
No Spread
1
16-pin (173 mil) TSSOP
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
3
4
5
6
S0
S1
Input Select pin 0. See Table1. Internal pull-up resistor.
Input Select pin 1. See Table 1. Internal pull-up resistor.
SS0
X1/ICLK
X2
Input Spread Select pin 0. See Table 2. Internal pull-up resistor.
Input Crystal or clock input. Connect to a 25 MHz crystal or single ended clock.
Output Crystal connection. Leave unconnected for clock input.
OE
Input Output enable tri-states outputs and device is not shut down. Internal
pull-up resistor.
7
8
9
GNDXD
SS1
Power Connect to ground.
Input Spread Select pin 1. See Table 2. Internal pull-up resistor.
IREF
Output Precision resistor attached to this pin is connected to the internal current
reference.
10
11
12
13
14
15
16
CLK1
CLK1
Output HCSL compliment clock output.
Output HCSL clock output.
VDDODA
GNDODA
CLK0
Power Connect to voltage supply +3.3 V for output driver and analog circuits
Power Connect to ground.
Output HCSL compliment clock output.
CLK0
Output HCSL clock output.
VDDXD
Power Connect to voltage supply +3.3 V for crystal oscillator and digital circuit.
MDS 557-03 E
2
Revision 061005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-03
PCI-EXPRESS CLOCK SOURCE
Applications Information
External Components
A minimum number of external components are
required for proper operation.
Output Structures
6*IREF
IREF
=2.3 mA
Decoupling Capacitors
Decoupling capacitors of 0.01 µF should be connected
between each VDD pin and the ground plane, as close
to the VDD pin as possible. Do not share ground vias
between components. Route power from power source
through the capacitor pad and then into ICS pin.
Crystal
See Output Termination
Sections - Pages 3 ~ 5
A 25 MHz fundamental mode parallel resonant crystal
should be used. This crystal must have less than 300
ppm of error across temperature in order for the
ICS557-03 to meet PCI Express specifications.
Ω
RR 475
General PCB Layout Recommendations
Crystal Capacitors
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
Crystal capacitors are connected from pins X1 to
ground and X2 to ground to optimize the accuracy of
the output frequency.
1. Each 0.01µF decoupling capacitor should be
mounted on the component side of the board as close
to the VDD pin as possible.
C = Crystal’s load capacitance in pF
L
Crystal Capacitors (pF) = (C - 8) * 2
L
For example, for a crystal with a 16 pF load cap, each
external crystal cap would be 16 pF. (16-8)*2=16.
2. No vias should be used between decoupling
capacitor and VDD pin.
Current Source (Iref) Reference Resistor - RR
3. The PCB trace to VDD pin should be kept as short
as possible, as should the PCB trace to the ground via.
Distance of the ferrite bead and bulk decoupling from
the device is less critical.
If board target trace impedance (Z) is 50Ω, then R =
R
475Ω (1%), providing IREF of 2.32 mA. The output
current (I ) is equal to 6*IREF.
OH
4. An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers (any ferrite beads and bulk decoupling
capacitors can be mounted on the back). Other signal
traces should be routed away from the ICS557-03.This
includes signal traces just underneath the device, or on
layers adjacent to the ground plane layer used by the
device.
Output Termination
The PCI-Express differential clock outputs of the
ICS557-03 are open source drivers and require an
external series resistor and a resistor to ground. These
resistor values and their allowable locations are shown
in detail in the PCI-Express Layout Guidelines
section.
The ICS557-03 can also be configured for LVDS
compatible voltage levels. See the LVDS Compatible
Layout Guidelines section.
MDS 557-03 E
3
Revision 061005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-03
PCI-EXPRESS CLOCK SOURCE
PCI-Express Layout Guidelines
Common Recommendations for Differential Routing
Dimension or Value Unit
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
L3 length, Route as non-coupled 50 ohm trace.
RS
RT
0.5 max
0.2 max
0.2 max
33
inch
inch
inch
ohm
ohm
49.9
Differential Routing on a Single PCB
Dimension or Value Unit
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
2 min to 16 max
1.8 min to 14.4 max
inch
inch
Differential Routing to a PCI Express Connector
L4 length, Route as coupled microstrip 100 ohm differential trace.
L4 length, Route as coupled stripline 100 ohm differential trace.
Dimension or Value Unit
0.25 to 14 max inch
0.225 min to 12.6 max inch
PCI-Express Device Routing
L1
L2
L4
RS
RS
L4’
L1’
L2’
RT
RT
PCI-Express
Load or
Connector
ICS557-03
Output
L3’ L3
Clock
Typical PCI-Express (HCSL)
Waveform
700 mV
0
500 ps
500 ps
tOR
tOF
0.52 V
0.175 V
0.52 V
0.175 V
MDS 557-03 E
4
Revision 061005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-03
PCI-EXPRESS CLOCK SOURCE
LVDS Compatible Layout Guidelines
LVDS Recommendations for Differential Routing
Dimension or Value Unit
L1 length, Route as non-coupled 50 ohm trace.
L2 length, Route as non-coupled 50 ohm trace.
RP
RQ
0.5 max
0.2 max
100
100
150
inch
inch
ohm
ohm
ohm
RT
L3 length, Route as coupled 50 ohm differential trace.
L3 length, Route as coupled 50 ohm differential trace.
LVDS Device Routing
L1
L3
RQ
RP
L3’
L1’
RT
RT
ICS557-03
Clock
Output
LVDS
Device
Load
L2’ L2
Typical LVDS Waveform
1325 mV
1000 mV
500 ps
500 ps
tOR
tOF
1250 mV
1150 mV
1250 mV
1150 mV
MDS 557-03 E
5
Revision 061005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-03
PCI-EXPRESS CLOCK SOURCE
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS557-03. These ratings are
stress ratings only. Functional operation of the device at these or any other conditions above those
indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods can affect product reliability. Electrical parameters are guaranteed
only over the recommended operating temperature range.
Item
Rating
Supply Voltage, VDD, VDDA
5.5 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
0 to +70°C
Ambient Operating Temperature (commercial)
Ambient Operating Temperature (industrial)
Storage Temperature
-40 to +85°C
-65 to +150°C
125°C
Junction Temperature
Soldering Temperature
260°C
ESD Protection (Input)
2000 V min. (HBM)
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 10%, Ambient Temperature -40 to +85°C
Parameter
Supply Voltage
Input High Voltage
Symbol
Conditions
Min.
2.97
Typ.
Max.
Units
V
3.3
3.63
1
V
S0, S1, OE, CLK, SS0, SS1
S0, S1, OE, CLK, SS0, SS1
0 < Vin < VDD
2.0
VDD +0.3
V
IH
1
Input Low Voltage
V
VSS-0.3
-5
0.8
5
V
IL
2
Input Leakage Current
I
µA
mA
mA
pF
pF
nH
kΩ
kΩ
IL
Operating Supply Current
I
50Ω, 2pF
65
35
7
DD
I
OE =Low
DDOE
Input Capacitance
Output Capacitance
Pin Inductance
C
Input pin capacitance
Output pin capacitance
IN
C
6
OUT
L
5
PIN
Output Resistance
Pull-up Resistor
R
CLKOUT
3.0
OUT
R
100
PU
1 Single edge is monotonic when transitioning through region.
2 Inputs with pull-ups/-downs are not included.
MDS 557-03 E
6
Revision 061005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-03
PCI-EXPRESS CLOCK SOURCE
AC Electrical Characteristics - CLK0/CLK1, CLK0/CLK1
Unless stated otherwise, VDD=3.3 V 10%, Ambient Temperature -40 to +85°C
Parameter
Input Frequency
Symbol
Conditions
Min.
Typ.
Max.
Units
MHz
MHz
mV
25
Output Frequency
Output High Voltage
25
200
850
1,2
1,2
V
Notes 1, 2
Notes 1, 2
660
-150
250
700
0
OH
Output Low Voltage
Crossing Point
V
mV
OL
Absolute, Notes 1, 2
350
550
140
mV
1,2
Voltage
Crossing Point
Variation over all edges, Notes 1, 2, 4
mV
1,2,4
Voltage
1,3
Jitter, Cycle-to-Cycle
Notes 1, 3
60
ps
kHz
ps
Modulation Frequency
Spread spectrum
30
31.5
332
344
33
1,2
Rise Time
t
From 0.175 V to 0.525 V, Notes 1, 2
From 0.525 V to 0.175 V, Notes 1, 2
Notes 1, 2
175
175
700
700
125
OR
1,2
Fall Time
t
ps
OF
Rise/Fall Time
ps
1,2
Variation
Skew between outputs
At VDD/2
50
55
ps
%
1,3
Duty Cycle
Notes 1, 3
45
5
Output Enable Time
All outputs, Note 5
All outputs, Note 5
From power-up VDD=3.3 V
Settling period after spread change
10
10
us
us
ms
ms
5
Output Disable Time
Stabilization Time
t
3.0
3.0
STABLE
Spread Change Time
t
SPREAD
Note 1: Test setup is R =50 ohms with 2 pF, Rr = 475Ω (1%).
L
Note 2: Measurement taken from a single-ended waveform.
Note 3: Measurement taken from a differential waveform.
Note 4: Measured at the crossing point where instantaneous voltages of both CLK and CLK are equal.
Note 5: CLK pins are tri-stated when OE is low asserted. CLK is driven differential when OE is high.
MDS 557-03 E
7
Revision 061005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-03
PCI-EXPRESS CLOCK SOURCE
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
78
70
68
37
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
Marking Diagram (ICS557G-03)
Marking Diagram (ICS557GI-03)
16
9
16
9
######
YYWW
557GI-03
######
YYWW
557G-03
ICS
ICS
1
8
1
8
Marking Diagram (ICS557G-03LF)
Marking Diagram (ICS557GI-03LF)
16
9
16
9
######
YYWW
######
YYWW
ICS
ICS
557G03LF
557GI03L
1
8
1
8
Notes:
1. ###### is the lot code.
2. YYWW is the last two digits of the year, and the week number that the part was assembled.
3. “LF” designates Pb (lead) free package.
4. “I” deisgnates industrial temperature range.
5. Bottom marking: (origin). Origin = country of origin of not USA.
MDS 557-03 E
8
Revision 061005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS557-03
PCI-EXPRESS CLOCK SOURCE
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
16
Millimeters
Min Max
Inches
Max
Symbol
Min
--
A
A1
A2
b
C
D
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
1
2
E
E1
e
6.40 BASIC
4.30
4.50
D
0.65 Basic
L
α
0.45
0°
0.75
8°
0.018
0°
0.030
8°
A
A2
aaa
--
0.10
--
0.004
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking
See Page 8
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
ICS557G-03
ICS557G-03T
ICS557G-03LF
ICS557G-03LFT
ICS557GI-03
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
16-pin TSSOP
Tape and Reel
Tubes
0 to +70° C
0 to +70° C
Tape and Reel
Tubes
0 to +70° C
See Page 8
-40 to +85° C
-40 to +85° C
-40 to +85° C
-40 to +85° C
ICS557GI-03T
ICS557GI-03LF
ICS557GI-03LFT
Tape and Reel
Tubes
Tape and Reel
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 557-03 E
9
Revision 061005
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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