ICS558G-02 [ICSI]
LVHSTL TO CMOS CLOCK DIVIDER; LVHSTL TO CMOS时钟分频器
| 型号： | ICS558G-02 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LVHSTL TO CMOS CLOCK DIVIDER |
| 文件： | 总5页 (文件大小：120K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS558-02
LVHSTL TO CMOS CLOCK DIVIDER
Description
Features
The ICS558-02 accepts a high-speed LVHSTL input
and provides four CMOS low skew outputs from a
selectable internal divider (divide by 3, divide by 4). The
four outputs are split into two banks of two outputs.
Each bank has a separate output enable to tri-state the
output buffers.
• 16-pin TSSOP package
• LVHSTL inputs
• Accepts up to 250 MHz input frequency
• Four low skew (<250 ps) outputs
• Selectable internal divider of 3 or 4
• Operating voltage of 3.3 V
TM
The ICS558-02 is a member of the ICS Clock Blocks
family of clock generation, synchronization, and
distribution devices.
Block Diagram
VDD
OE0
4
CLK1
CLK2
HCLK
HCLK
Output Divide
/3 or /4
CLK3
CLK4
SEL
3
OE1
GND
MDS 558-02 D
1
Revision 020504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS558-02
LVHSTL TO CMOS CLOCK DIVIDER
Tri-State Table
Pin Assignment
OE1 OE0
CLK 1, CLK 2
Tri-state
CLK 3, CLK 4
Tri-state
SEL
VDD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VDD
VDD
CLK1
CLK2
CLK3
CLK4
GND
OE1
0
0
1
1
0
1
0
1
Clock ON
Tri-state
Tri-state
VDD
Clock ON
Clock ON
HCLK
HCLK
GND
GND
OE0
Clock ON
Output Divide Selection
SEL
0
Output Divide
/3
/4
16 Pin 173 Mil (0.65mm) TSSOP
1
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
Select pin for output divider. See table above. Internal pull-up to VDD.
1
2
3
4
5
6
7
8
SEL
VDD
VDD
HCLK
HCLK
GND
GND
OE0
Input
Power Connect to +3.3 V.
Power Connect to +3.3 V.
Input
Input
Differential LVHSTL input (true input).
Differential LVHSTL input (complimentary input).
Power Connect to ground.
Power Connect to ground.
Input
Output enable for CLK1 and CLK2. See table above. Internal pull-up
to VDD.
9
OE1
Input
Output enable for CLK3 and CLK4. See table above. Internal pull-up
to VDD.
10
11
12
13
14
15
16
GND
CLK4
CLK3
CLK2
CLK1
VDD
Power Connect to ground.
Output Low skew clock output.
Output Low skew clock output.
Output Low skew clock output.
Output Low skew clock output.
Power Connect to +3.3 V.
VDD
Power Connect to +3.3 V.
MDS 558-02 D
2
Revision 020504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS558-02
LVHSTL TO CMOS CLOCK DIVIDER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS558-02. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage
4.6 V
All Inputs and Outputs
-0.5 V to VDD+0.5 V
0 to +70 °C
-65 to +150 °C
125 °C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature
260 °C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+70
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
0
+3.15
+3.3
+3.5
V
DC Electrical Characteristics
VDD=3.3 V 5ꢀ, Ambient temperature 0 to +70°C, unless stated otherwise stated.
Parameter
Operating Voltage
Symbol
VDD
Conditions
Min.
Typ.
3.3
Max.
Units
3.135
3.465
V
mA
V
Operating Supply Current
Input High Voltage
IDD
No load, 100 MHz
OE pins
OE pins
HCLK
60
V
VDD-0.5
VDD
0.5
IH
Input Low Voltage
V
V
IL
Input High Voltage
V
Vx + 0.1
-0.3
1.2
V
IH
Input Low Voltage
V
HCLK
Vx - 0.1
1.0
V
IL
Peak to Peak Input Voltage
HCLK
0.3
V
HCLK Input Leakage
Current
I
-20
20
µA
IL
Input Common Mode
Voltage
Vx
Input Common Mode
0.68
2.4
0.90
0.4
V
Output High Voltage
Output Low Voltage
V
I
I
= -14.5 mA
= 9.4 mA
V
V
OH
OH
OL
V
OL
MDS 558-02 D
3
Revision 020504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS558-02
LVHSTL TO CMOS CLOCK DIVIDER
Parameter
Symbol
Conditions
Min.
Typ.
20
Max.
Units
Ω
Nominal Output Impedance
Internal Pull-up Resistor
Input Capacitance
Z
O
R
250
7
kΩ
PU
C
pF
IN
AC Electrical Characteristics
VDD = 3.3 V 5ꢀ, Ambient Temperature 0 to +70°C, unless stated otherwise stated.
Parameter
Symbol
Conditions
Min.
0
Typ. Max. Units
Input Frequency
250
2.0
MHz
ns
Output Rise Time
Output Fall Time
t
0.4 to 2.4 V, C =30 pF
0.5
0.5
1.1
1.0
0
OR
L
t
2.4 to 0.4 V, C =30 pF
2.0
ns
OF
L
Skew (between any two output
clocks)
30 pF load
250
ps
Propagation Delay
9
12
55
ns
%
Output Clock Duty Cycle
at VDD/2, C =30 pF
45
50
L
Thermal Characteristics (16-pin TSSOP)
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
78
70
68
37
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
MDS 558-02 D
4
Revision 020504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS558-02
LVHSTL TO CMOS CLOCK DIVIDER
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95, MO-153
Millimeters
Min Max
Inches
Max
16
Symbol
Min
--
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
C
D
E
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
6.40 BASIC
4.30 4.50
0.65 Basic
1
2
E1
e
L
D
0.45
0°
0.75
8°
0.018
0°
0.030
8°
α
aaa
--
0.10
--
0.004
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
Marking (both)
Shipping
packaging
Tubes
Package
Temperature
ICS558G-02
ICS558G-02
ICS558G-02
16-pin TSSOP
16-pin TSSOP
0 to 70°C
0 to 70°C
ICS558G-02T
Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit
Systems (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of
third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended
temperature range, high reliability, or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice.
ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 558-02 D
5
Revision 020504
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
相关型号：
ICS558G-02LFT
Low Skew Clock Driver, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.173 INCH, MO-153, TSSOP-16
IDT
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