ICS570AIT [ICSI]
Multiplier and Zero Delay Buffer; 乘法器和零延迟缓冲器
| 型号： | ICS570AIT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Multiplier and Zero Delay Buffer |
| 文件： | 总6页 (文件大小：89K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS570A
Multiplier and Zero Delay Buffer
Description
Features
The ICS570A is a high performance Zero Delay
Buffer (ZDB) which integrates ICS’ proprietary
analog/digital Phase Locked Loop (PLL) techniques.
ICS introduced the world standard for these devices
in 1992 with the debut of the AV9170. The
ICS570A, part of ICS’ ClockBlocks™ family, was
designed as a performance upgrade to meet today’s
higher speed and lower voltage requirements. The
zero delay feature means that the rising edge of the
input clock aligns with the rising edges of both
outputs, giving the appearance of no delay through
the device. There are two outputs on the chip, one
being a low-skew divide by two of the other. The chip
has an all-chip power down/tri-state mode that stops
the internal PLL and puts both outputs into the high
impedance state.
• Packaged in 8 pin SOIC.
• Pin-for-pin replacement and upgrade to ICS570
• Functional equivalent to AV9170 (not a pin-
for-pin replacement).
• Low input to output skew of 500 ps max.
• Low skew (250 ps) outputs. One is ÷ 2 of other.
• Ability to choose between 14 different
multipliers from 0.5X to 32X.
• Input clock frequency up to 150 MHz at 3.3V.
• Can recover poor input clock duty cycle.
• Output clock duty cycle of 45/55.
• Power Down and Tri-State Mode.
• Full CMOS clock swings with 25mA drive
capability at TTL levels.
The chip is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to video. By allowing off-chip
feedback paths, the ICS570A can eliminate the delay
through other devices.
• Advanced, low power CMOS process.
• Operating voltage of 3.0 to 5.5 V.
• Industrial temperature version available
The ICS570A was done to improve jitter from the
original ICS570, and so it is recommended for all new
designs.
Block Diagram
Voltage
Output
ICLK
S1, S0
Phase
Detector,
Charge
Pump, and
Loop Filter
CLK
Controlled
Oscillator
Buffer
2
÷2
divide by
N
Output
Buffer
FBIN
CLK/2
External feedback can come from CLK or CLK/2 (see table on page 2).
MDS 570A C
1
Revision 102700
Printed 11/14/00
Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com
ICS570A
Multiplier and Zero Delay Buffer
Clock Multiplier Decoding Table
(Multiplies input clock by shown amount)
Pin Assignment
FBIN from CLK FBIN from CLK/2 ICLK Input Range
1
8
7
6
5
CLK/2
CLK
S0
S1
S1
#1
0
S0
#6
0
CLK
CLK/2
CLK
CLK/2
FB from CLK/2 *
pin # 7 pin # 8 pin # 7 pin # 8
Power Down and Tri-State
(3.3V, MHz)
-
2
VDD
3
4
0
M
1
x3
x4
x1.5
x2
x6
x8
x3
x4
2.5 to 25
2.5 to 19
2.5 to 9.5
2.5 to 12.5
2.5 to 7.5
5 to 75
GND
ICLK
0
FBIN
M
M
M
1
0
x8
x4
x16
x12
x20
x2
x8
M
1
x6
x3
x6
8 pin SOIC
x10
x1
x5
x10
x1
0
÷2
x8
1
M
1
x16
x2
x32
x4
x16
x2
2.5 to 5
1
x1
2.5 to 37.5
0 = connect directly to ground.
M = leave unconnected (self-biases to VDD/2).
1 = connect directly to VDD.
*Input range with CLK feedback is double that for CLK/2.
Pin Descriptions
Number
Name
S1
Type Description
1
2
3
4
5
6
7
8
I
P
Select 1 for output clock. Connect to GND, VDD, or float per decoding table above.
Connect to +3.3V or +5V.
VDD
GND
ICLK
FBIN
S0
P
Connect to ground.
CI
CI
I
Reference clock input.
Feedback clock input.
Select 0 for output clock. Connect to GND, VDD, or float per decoding table above.
Clock output per Table above.
CLK
CLK/2
O
O
Clock output per Table above. Low skew divide by two of pin 7 clock.
Key: CI = clock input, I = input, O = output, P = power supply connection
External Components
The ICS570A requires a 0.01 µF decoupling capacitor to be connected between VDD and GND. It must
be connected close to the ICS570A to minimize lead inductance. No external power supply filtering is
required for this device. A 27 Wterminating resistor can be used next to each output pin.
MDS 570A C
2
Revision 102700
Printed 11/14/00
Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com
ICS570A
Multiplier and Zero Delay Buffer
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Referenced to GND
Referenced to GND
Referenced to GND
ICS570M
7
VDD+0.5
VDD+0.5
70
V
V
Inputs
-0.5
-0.5
0
Clock Output
V
Ambient Operating Temperature
°C
°C
°C
°C
ICS570MI
-40
85
Soldering Temperature
Storage temperature
Max of 10 seconds
260
-65
150
DC CHARACTERISTICS (VDD = 3.3V or 5.0V unless otherwise noted)
Operating Voltage, VDD
3
2
5.5
0.8
V
V
Input High Voltage, VIH, VDD=5V
Input Low Voltage, VIL, VDD=5V
Input High Voltage, VIH
ICLK, FBIN
ICLK, FBIN
S0, S1
V
VDD-0.5
V
Input High Voltage, VIM (mid-level)
Input Low Voltage, VIL
S0, S1
VDD/2
V
S0, S1
0.5
0.4
V
Output High Voltage, VOH, CMOS level
Output High Voltage, VOH
IOH=-4mA
IOH=-12mA
IOL=12mA
No Load, 5.0V
No Load, 3.3V
Each Output
VDD-0.4
2.4
V
V
Output Low Voltage, VOL
V
IDD Operating Supply Current, 50 in, 100 out
IDD Operating Supply Current, 50 in, 100 out
Short Circuit Current
22
12
±50
5
mA
mA
mA
pF
Input Capacitance, S1, S0
AC CHARACTERISTICS (VDD = 3.3V or 5.0V unless otherwise noted)
Input Frequency, ICLK (see table on page 2)
2.5
10
150
150
150
500
1.0
MH z
MH z
ps
Output Clock Frequency, CLK
Skew of output clocks
Note 2
50
Input skew, ICLK to FBIN Note 2
Input skew, ICLK to FBIN Note 2
Input skew, ICLK to FBIN Note 2
Input skew, ICLK to FBIN Note 2
Input skew, ICLK to FBIN Note 2
Output Clock Rise Time, 3.3V
Output Clock Fall Time, 3.3V
Output Clock Rise Time, 5V
Output Clock Fall Time, 5V
Output Clock Duty Cycle
VDD=3.3V, CLK>10MHz
VDD=3.3V, CLK<5MHz
VDD=3.3V, CLK<10MHz
VDD=5V, CLK<10MHz
VDD=5V, CLK>10MHz
0.8 to 2.0V, note 3
2.0 to 0.8V, note 3
0.8 to 2.0V, note 3
2.0 to 0.8V, note 3
at VDD/2
-500
-1.0
-750
-1.5
-1.0
ps
ns
750
1.5
ps
ns
1.0
ns
0.75
0.75
ns
ns
0.5
ns
0.5
ns
45
49 to 51
55
%
Notes 1. Stresses beyond these can permanently damage the device
2. Assumes clocks with same rise time, measured from rising edges at VDD/2.
3. With 27 W terminating resistor and 15 pF loads.
MDS 570A C
3
Revision 102700
Printed 11/14/00
Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com
ICS570A
Multiplier and Zero Delay Buffer
All jitter values measured at 25 °C with 27Wseries termination resistors and 15pF loads on both CLK and
CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left
unconnected. This will give lower output jitter.
One Sigma Clock Period Jitter (ps), VDD = 3.3 V
CLK
CLK/2
CLK Frequency (MHz)
CLK/2 Frequency (MHz)
ICLK
Frequency
(MHz)
ICLK
Frequency
(MHz)
20 - 50
70
>50
85
<20
145
100
—
10 - 25
100
70
>25
20
<10
200
<5
<5
5 - 10
>10
65
85
85
5 - 10 135
20
20
50
—
>10
50
Absolute Clock Period Jitter (ps), VDD = 3.3V
CLK
CLK/2
CLK Frequency (MHz)
ICLK
Frequency
CLK/2 Frequency (MHz)
ICLK
Frequency
(MHz)
(MHz)
<10
>50
10 - 25
>25
<20
±850
±370
—
20 - 50
±350
<5
<5
±1100 ±600
±180
±180
±180
±90
±90
±90
±270
±350
±500
5 - 10
>10
5 - 10
>10
±140
±160
—
One Sigma Clock Period Jitter (ps), VDD = 5 V
CLK
CLK/2
CLK/2 Frequency (MHz)
CLK Frequency (MHz)
ICLK
Frequency
(MHz)
ICLK
Frequency
(MHz)
10 - 25
>25
20 - 50
>50
120
120
120
<10
50
<20
130
<5
25
35
30
<5
100
100
20
20
25
5 - 10
>10
5 - 10 120
60
—
—
>10
70
Absolute Clock Period Jitter (ps), VDD = 5 V
CLK
CLK/2
CLK Frequency (MHz)
CLK/2 Frequency (MHz)
ICLK
Frequency
(MHz)
ICLK
Frequency
(MHz)
10 - 25
±100
>25
<20
20 - 50
±180
>50
<10
<5
±270
<5
±170
±230
±230
±230
±50
±80
±90
±220
5 - 10
>10
5 - 10
>10
±100
±270
—
±210
—
±160
±100
MDS 570A C
4
Revision 102700
Printed 11/14/00
Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com
ICS570A
Multiplier and Zero Delay Buffer
Recommended Circuit:
S1
CLK
VDD
GND
CLK/2
S0
INPUT
FBIN
ICLK
ICK
CLK
CLK
CLK/2
CLK/2
x2 Mode (S1, S0 = 1, 0)
CLK/2 Feedback
x2 Mode (S1, S0 = 1, 1)
CLK Feedback
Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK. But the
CLK/2 could be a falling edge compared with ICLK. Therefore, wherever possible, we recommend the use of
CLK/2 feedback. This will synchronize the rising edges of all 3 clocks.
MDS 570A C
5
Revision 102700
Printed 11/14/00
Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com
ICS570A
Multiplier and Zero Delay Buffer
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
8 pin SOIC
JEDEC Dimensions Millimeters
Symbol
Min
0.0532 0.0688
0.004 0.0098
Max
Min
1.35
0.10
0.33
0.19
4.80
3.80
1.27 BSC
5.80
0.25
0.41
Max
1.75
0.25
0.51
0.25
5.00
4.00
A
A1
B
C
D
E
0.0130 0.0200
0.0075 0.0098
0.1890 0.1968
0.1497 0.1574
.050 BSC
E
H
INDEX
AREA
e
H
h
0.2284 0.2440
0.0099 0.0195
0.0160 0.0500
6.20
0.50
1.27
L
h x 45°
D
A
A1
C
B
e
L
Ordering Information
Part/Order Number
ICS570A
Marking
ICS570A
ICS570A
ICS570AI
ICS570AI
ICS570M
ICS570M
ICS570I
Package
8 pin SOIC
8 pin SOIC on tape and reel
8 pin SOIC
8 pin SOIC on tape and reel
8 pin SOIC
8 pin SOIC on tape and reel
8 pin SOIC
8 pin SOIC on tape and reel
Temperature
0 to 70 °C
0 to 70 °C
-40 to +85 °C
-40 to +85 °C
0 to 70 °C
0 to 70 °C
-40 to +85 °C
-40 to +85 °C
ICS570AT
ICS570AI
ICS570AIT
ICS570M
ICS570MT
ICS570MI
ICS570MIT
ICS570I
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any
ICS product for use in life support devices or critical medical instruments.
ClockBlocks is a trademark of ICS
MDS 570A C
6
Revision 102700
Printed 11/14/00
Integrated Circuit Systems, Inc .• 525 Race Street • San Jose • CA •95126• (408)295-9800tel •www.icst.com
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