ICS570BI [ICSI]
Multiplier and Zero Delay Buffer; 乘法器和零延迟缓冲器
| 型号： | ICS570BI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Multiplier and Zero Delay Buffer |
| 文件： | 总6页 (文件大小：99K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY INFORMATION
ICS570B
Multiplier and Zero Delay Buffer
Description
Features
• Packaged in 8 pin SOIC.
The ICS570B is a high performance Zero Delay Buffer
(ZDB) which integrates ICS’ proprietary analog/digital
Phase Locked Loop (PLL) techniques. The ICS570B,
part of ICS’ ClockBlocks™ family, was designed as a
performance upgrade to meet today’s higher speed and
lower voltage requirements. The zero delay feature
means that the rising edge of the input clock aligns with
the rising edges of both outputs, giving the appearance
of no delay through the device. There are two outputs on
the chip, one being a low-skew divide by two of the other.
The device incorporates an all-chip power down/tri-state
mode that stops the internal PLL and puts both outputs
into a high impedance state.
• Pin-for-pin replacement and upgrade to
ICS570/ICS570A
• Functional equivalent to AV9170 (not a pin-
for-pin replacement).
• Low input to output skew of 300 ps max (>60 MHz
outputs).
• Low skew (100 ps) outputs.
• Ability to choose between 14 different
multipliers from 0.5X to 32X.
• Input clock frequency up to 150 MHz at 3.3V.
• Can recover degraded input clock duty cycle.
• Output clock duty cycle of 45/55.
• Power Down and Tri-State Mode.
• Full CMOS clock swings with 25mA drive
capability at TTL levels.
The ICS570B is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to graphics/video. By allowing off-chip
feedback paths, the device can eliminate the delay
through other devices.
The ICS570B was done to improve input to output jitter
from the original ICS570M and ICS570A verisons, and is
recommended for all new 3.3 V only designs.
• Advanced, low power CMOS process.
• Operating voltage of 3.3 V (±5%).
• Industrial temperature version available
For 5V applications, use the ICS570A.
Block Diagram
Voltage
Output
ICLK
Phase
Detector,
Charge
Controlled
Oscillator
CLK
Buffer
2
S1, S0
Pump, and
Loop Filter
÷2
divide by N
Output
Buffer
FBIN
CLK/2
External feedback can come from CLK or CLK/2 (see table on page 2).
MDS 570B A
1
Revision 053001
Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
PRELIMINARY INFORMATION
ICS570B
Multiplier and Zero Delay Buffer
Pin Assignment
1
2
3
4
8
7
6
5
CLK/2
CLK
S0
S1
VDD
GND
ICLK
FBIN
8 pin 150 mil SOIC
Clock Multiplier Decoding Table
(Multiplies input clock by shown amount)
FBIN from CLK FBIN from CLK/2 25°C ICLK Input Range
85°C ICLK Input Range
FB from CLK/2 *
(3.3V, MHz)
-
S1 S0
CLK
CLK/2
CLK
CLK/2
FB from CLK/2 *
(3.3V, MHz)
-
#1 #6 pin # 7 pin # 8 pin # 7 pin # 8
0
0
0
M
1
Power Down and Tri-State
x3
x4
x1.5
x2
x6
x8
x3
x4
2.5 to 25
2.5 to 19
2.5 to 9.5
2.5 to 12.5
2.5 to 7.5
5 to 75
3 to 25
0
2.5 to 19
M
M
M
1
0
x8
x4
x16
x12
x20
x2
x8
2.5 to 9.5
2.5 to 12.5
2.5 to 7.5
8 to 75
M
1
x6
x3
x6
x10
x1
x5
x10
x1
0
÷2
x8
1
M
1
x16
x2
x32
x4
x16
x2
2.5 to 5
2.5 to 5
1
x1
2.5 to 37.5
4.5 to 37.5
0 = connect directly to ground.
M = leave unconnected (self-biases to VDD/2).
1 = connect directly to VDD.
*Input range with CLK feedback is double that for CLK/2.
Pin Descriptions
Number
Name
S1
Type Description
1
2
3
4
5
6
7
8
I
P
P
CI
CI
I
Select 1 for output clock. Connect to GND, VDD, or float per decoding table above.
Connect to +3.3V.
VDD
GND
ICLK
FBIN
S0
Connect to ground.
Reference clock input.
Feedback clock input.
Select 0 for output clock. Connect to GND, VDD, or float per decoding table above.
Clock output per table above.
CLK
CLK/2
O
O
Clock output per table above. Low skew divide by two of pin 7 clock.
Key: CI = clock input, I = input, O = output, P = power supply connection
External Components
The ICS570B requires a 0.01 µF decoupling capacitor to be connected between VDD and GND. It must be
connected close to the ICS570B to minimize lead inductance. No external power supply filtering is required for this
device. A 27 W series terminating resistor can be used next to each output pin.
MDS 570B A
2
Revision 053001
Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
PRELIMINARY INFORMATION
ICS570B
Multiplier and Zero Delay Buffer
Electrical Specifications
Parameter
Conditions
Minimum Typical Maximum
Units
ABSOLUTE MAXIMUM RATINGS (Note 1)
Supply Voltage, VDD
Inputs
Referenced to GND
Referenced to GND
Referenced to GND
ICS570B
7
V
V
-0.5
-0.5
0
VDD+0.5
VDD+0.5
70
Clock Output
V
Ambient Operating Temperature
°C
°C
°C
°C
ICS570BI
-40
85
Soldering Temperature
Max of 10 seconds
260
Storage temperature
-65
150
DC CHARACTERISTICS (VDD = 3.3V)
Operating Voltage, VDD
3.15
2
3.45
0.8
V
V
Input High Voltage, VIH
ICLK, FBIN
ICLK, FBIN
S0, S1
Input Low Voltage, VIL
V
Input High Voltage, VIH
VDD-0.5
V
Input High Voltage, VIM (mid-level)
Input Low Voltage, VIL
S0, S1
VDD/2
V
S0, S1
0.5
0.4
V
Output High Voltage, VOH, CMOS level
Output High Voltage, VOH
IOH=-4mA
IOH=-12mA
IOL=12mA
No Load, 3.3V
Each Output
VDD-0.4
2.4
V
V
Output Low Voltage, VOL
V
IDD Operating Supply Current, 50 in, 100 out
Short Circuit Current
16
±100
5
mA
mA
pF
Input Capacitance, S1, S0
AC CHARACTERISTICS (VDD = 3.3V)
Input Frequency, ICLK (see table on page 2)
Output Clock Frequency, CLK
Output to output skew
FBIN from CLK/2
See Table on Page 2
150
10
MHz
ps
ps
ps
ps
ns
ns
%
Note 2
100
175
Input to Output Jitter
40-150 MHz
100-250
Input skew, ICLK to FBIN Note 2
Input skew, ICLK to FBIN Note 2
Output Clock Rise Time, 3.3V
Output Clock Fall Time, 3.3V
Output Clock Duty Cycle
CLK>30MHz
-300
-600
300
600
VDD=3.3V, CLK<10MHz
0.8 to 2.0V, note 3
2.0 to 0.8V, note 3
at VDD/2
0.75
0.75
45
49 to 51
55
Notes
1. Stresses beyond these can permanently damage the device
2. Assumes clocks with same rise time, measured from rising edges at VDD/2.
3. With 27 Wterminating resistor and 15 pF loads.
MDS 570B A
3
Revision 053001
Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
PRELIMINARY INFORMATION
ICS570B
Multiplier and Zero Delay Buffer
Clock Period Jitter Tables
All jitter values are considered typical measured at 25°C with 27W series termination resistor and 15pF loads on
both CLK and CLK2. The feedback is from CLK2 to FBIN. Note that if an output is unused, it should be left
unconnected to improve output jitter on the active output clocks.
Absolute and One Sigma Jitter (ps), VDD = 3.3V
CLKIN
(MHz) MultiplierAbsolute 1 sigma Multiplier Absolute
CLK = 50M
CLK/2 = 25M
S1
0
S0
M
1
1 sigma
20
8.333
6.25
6x
8x
±110
±125
±130
±120
±115
±130
±120
±120
80
90
90
90
90
50
90
60
3x
4x
±55
±50
±55
±55
±55
±55
±55
±55
0
20
M
M
M
1
0
3.125
4.167
2.5
16x
12x
20x
2x
8x
20
M
1
6x
20
10x
1x
20
0
25
20
1
M
1
1.5625
12.5
32x
4x
16x
2x
20
1
20
Absolute and One Sigma Jitter (ps), VDD = 3.3V
CLKIN
(MHz) MultiplierAbsolute 1 sigma Multiplier Absolute
CLK = 100M
CLK/2 = 50M
S1
0
S0
M
1
1 sigma
20
16.667
12.5
6.25
8.333
5
6x
8x
±100
±100
±110
±100
±105
±90
70
70
80
70
70
60
70
70
3x
4x
±45
±45
±45
±45
±40
±40
±45
±60
0
20
M
M
M
1
0
16x
12x
20x
2x
8x
20
M
1
6x
20
10x
1x
20
0
50
20
1
M
1
3.125
25
32x
4x
±95
16x
2x
20
1
±105
30
Absolute and One Sigma Jitter (ps), VDD = 3.3V
CLKIN
CLK = 150M
CLK/2 = 75M
S1
0
S0
M
1
(MHz) MultiplierAbsolute 1 sigma Multiplier Absolute
1 sigma
20
25
18.375
9.375
12.5
7.5
6x
8x
±115
±1 2 0
±130
±130
±130
±115
±130
±110
70
80
90
90
90
90
90
70
3x
4x
±50
±50
±50
±45
±45
±45
±50
±60
0
20
M
M
M
1
0
16x
12x
20x
2x
8x
20
M
1
6x
20
10x
1x
20
0
75
20
1
M
1
4.6875
37.5
32x
4x
16x
2x
20
1
20
MDS 570B A
4
Revision 053001
Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
PRELIMINARY INFORMATION
ICS570B
Multiplier and Zero Delay Buffer
Recommended Circuit:
S1
CLK
VDD
GND
CLK/2
S0
INPUT
FBIN
ICLK
ICK
CLK
CLK
CLK/2
CLK/2
x2 Mode (S1, S0 = 1, 0)
CLK/2 Feedback
x2 Mode (S1, S0 = 1, 1)
CLK Feedback
Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK. However, the CLK/2
could be a falling edge compared with ICLK. Therefore, whenever possible, we recommend the use of CLK/2 feedback.
This will synchronize the rising edges of all 3 clocks.
MDS 570B A
5
Revision 053001
Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
PRELIMINARY INFORMATION
ICS570B
Multiplier and Zero Delay Buffer
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
8 pin (150 mil) SOIC
Inches
Millimeters
Symbol
Min
Max
Min
1.35
0.10
0.33
0.19
4.80
3.80
Max
A
A1
B
0.0532
0.004
0.0688
0.0098
0.0200
0.0098
0.1968
0.1574
1.75
0.25
0.51
0.25
5.00
4.00
0.0130
0.0075
0.1890
0.1497
E
H
C
D
E
INDEX
AREA
e
.050 BSC
1.27 BSC
H
h
0.2284
0.0099
0.0160
0.2440
0.0195
0.0500
5.80
0.25
0.41
6.20
0.50
1.27
h x 45°
L
D
A
A1
C
B
e
L
Ordering Information
Part/Order Number
ICS570B
Marking
ICS570B
ICS570B
ICS570BI
ICS570BI
Package/Comments
8 pin SOIC
Temperature
0 to 70 °C
ICS570BT
8 pin SOIC on tape and reel
8 pin SOIC
0 to 70 °C
ICS570BI
-40 to +85 °C
-40 to +85 °C
ICS570BIT
8 pin SOIC on tape and reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits,patents,orlicensesareimplied. Thisproductisintendedforuseinnormalcommercialapplications.Anyotherapplicationssuchasthose
requiringextendedtemperaturerange,highreliability,orotherextraordinaryenvironmentalrequirementsarenotrecommendedwithoutadditional
processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
ClockBlocks is a trademark of ICS
MDS 570B A
6
Revision 053001
Integrated Circuit Systems, Inc . • 525 Race Street • San Jose • CA • 95126 • (408)295-9800tel • www.icst.com
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