ICS570BMLFT [IDT]
Clock Driver;
| 型号： | ICS570BMLFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Driver |
| 文件： | 总9页 (文件大小：198K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS570
Multiplier and Zero Delay Buffer
Description
Features
The ICS570 is a high-performance Zero Delay Buffer
(ZDB) which integrates ICS’ proprietary analog/digital
Phase Locked Loop (PLL) techniques. The A version is
recommended for 5 V designs and the B version for
3.3 V designs. The chip is part of ICS’ ClockBlocks
family, and was designed as a performance upgrade to
meet today’s higher speed and lower voltage
requirements. The zero delay feature means that the
rising edge of the input clock aligns with the rising
edges of both output clocks, giving the appearance of
no delay through the device. There are two outputs on
the chip, one being a low-skew divide by two of the
other output. The device incorporates an all-chip power
down/tri-state mode that stops the internal PLL and
puts both outputs into a high impedance state.
• 8-pin SOIC package
• Available in Pb (lead) free package (A and B versions
only)
• Pin-for-pin replacement and upgrade to ICS570M
TM
• Functional equivalent to AV9170 (not a pin-for-pin
replacement)
• Low input to output skew of 300 ps max (>60 MHz
outputs)
• Ability to choose between 14 different multipliers
from 0.5x to 32x
• Output clock frequency up to 168 MHz at 3.3 V
• Can recover degraded input clock duty cycle
• Output clock duty cycle of 45/55
• Power Down and Tri-State Mode
• Passes spread spectrum clock modulation
The ICS570 is ideal for synchronizing outputs in a large
variety of systems, from personal computers to data
communications to graphics/video. By allowing off-chip
feedback paths, the device can eliminate the delay
through other devices.
• Full CMOS clock swings with 25 mA drive capability
at TTL levels
• Advanced, low power CMOS process
• ICS570B has an operating voltage of 3.3 V ( 5%)
• ICS570A has an operating voltage of 5.0 V ( 5%)
• Industrial temperature version available
The ICS570 A and B versions were designed to
improve input to output jitter from the original ICS570M
version, and are recommended for all new designs.
Block Diagram
ICLK
S1:0
Phase
Detector,
Charge
Pum p,
VCO
CLK
/2
and Loop
Filter
CLK2
divide
by N
FBIN
External feedback can com e from CLK or CLK/2 (see table on page 2)
MDS 570 H
1
Revision 010605
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Pin Assignment
S1
VDD
GND
ICLK
8
7
6
5
1
2
3
4
CLK/2
CLK
S0
FBIN
8 pin (150 mil) SOIC
Clock Multiplier Decoding Table
(Multiplies Input clock by amount shown)
FBIN from CLK FBIN from CLK/2
S1 S0
ICS570B (3.3 V)
ICS570A (5.0 V)
CLK
CLK2
CLK
CLK2 ICLK Input Range FB from CLK/2* ICLK Input Range FB from CLK/2*
#1 #6 pin #7
pin #8
pin #7
pin #8
0
0
0
M
1
Power Down and Tri-State
-
-
x3
x4
x1.5
x2
x4
x3
x5
/2
x6
x8
x3
x4
3.75 to 28
2.75 to 19
2.5 to 9.5
2.5 to 12.5
2.5 to 7.5
11 to 75
2.5 to 25
2.5 to 19
2.5 to 9.5
2.5 to 12.5
2.5 to 7.5
5 to 75
0
M
M
M
1
0
x8
x16
x12
x20
x2
x8
M
1
x6
x6
x10
x1
x10
x1
0
1
M
x16
x8
x32
x4
x16
x2
2.5 to 5
2.5 to 5
1
1
x2
x1
5.5 to 37.5
2.5 to 37.5
0 = connect directly to ground
M = leave unconnected (self-biases to VDD/2)
1 = connect directly to VDD
*Input range with CLK feedback is double that for CLK/2
Pin Descriptions
Pin
Number
Pin
Name
Pin
Type
Pin Description
1
2
3
4
5
6
7
8
S1
VDD
GND
ICLK
FBIN
S0
Input
Power
Power
Input
Input
Input
Select 1 for output clock. Connect to GND, VDD, or float per decoding table above.
Connect to +3.3 V (ICS570B). Connect to +5.0 V (ICS570A).
Connect to ground.
Reference clock input.
Feedback clock input.
Select 0 for output clock. Connect to GND, VDD, or float per decoding table above.
CLK
CLK/2
Output Clock output per table above.
Output Clock output per table above. Low skew divide by two of pin 7 clock.
MDS 570 H
2
Revision 010605
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
External Components
The ICS570 requires a 0.01µF decoupling capacitor to be connected between VDD and GND. It must be
connected close to the part to minimize lead inductance. No external power supply filtering is required for
this device. A 33Ω series terminating resistor can be used next to each output pin.
Recommended Circuit
S1
CLK
VDD
CLK/2
ICLK
GND
S0
CLK
Input
FBIN
CLK/2
x2 Mode (S1, S0 = 1, 0)
CLK/2 Feedback
ICLK
CLK
CLK/2
x2 Mode (S1, S0 = 1, 1)
CLK Feedback
Using CLK as the feedback will always result in synchronized rising edges between ICLK and CLK.
However, the CLK/2 could be a falling edge compared with ICLK. ICS recommends using CLK/2 feedback
whenever possible. This will synchronize the rising edges of all three clocks.
MDS 570 H
3
Revision 010605
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Clock Period Jitter Tables (ICS570A)
All jitter values are considered typical measured at 25°C with 27Ω termination resistor and 15 pF loads on
both CLK and CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left
unconnected to improve output jitter on the active output clocks.
Absolute and One Sigma Jitter (ps)
CLK = 50M
P to P
115
CLK/2 = 25M
S1 S0 CLKIN (MHz)
Multiplier
6x
1 sigma
80
Multiplier
P to P
65
1 sigma
20
0
0
M
1
8.333
6.25
3x
4x
8x
115
80
60
20
M
M
M
1
0
3.125
4.167
2.5
16x
12x
20x
2x
120
80
8x
55
20
M
1
120
90
6x
60
20
120
80
10x
1x
60
20
0
25
120
70
55
20
1
M
1
1.5625
12.5
32x
4x
120
80
16x
2x
50
20
1
120
80
55
20
Absolute and One Sigma Jitter (ps)
CLK = 100M
P to P
135
CLK/2 = 50M
S1 S0 CLKIN (MHz)
Multiplier
6x
1 sigma
100
100
110
110
100
90
Multiplier
P to P
55
1 sigma
20
0
0
M
1
16.667
12.5
6.25
8.333
5
3x
4x
8x
140
50
20
M
M
M
1
0
16x
12x
20x
2x
140
8x
55
20
M
1
140
6x
55
20
135
10x
1x
50
20
0
50
120
50
20
1
M
1
3.125
25
32x
4x
135
100
90
16x
2x
55
20
1
130
65
20
Absolute and One Sigma Jitter (ps)
CLK = 150M
CLK/2 = 75M
S1 S0 CLKIN (MHz)
Multiplier
6x
P to P
160
165
170
160
160
155
165
160
1 sigma
120
Multiplier
P to P
55
1 sigma
20
0
0
M
1
25
18.375
9.375
12.5
7.5
3x
4x
8x
120
55
20
M
M
M
1
0
16x
12x
20x
2x
120
8x
50
20
M
1
120
6x
55
20
120
10x
1x
55
20
0
75
110
55
20
1
M
1
4.6875
37.5
32x
4x
120
16x
2x
55
20
1
110
50
20
MDS 570 H
4
Revision 010605
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Clock Period Jitter Tables (ICS570B)
All jitter values are considered typical measured at 25°C with 27Ω termination resistor and 15 pF loads on
both CLK and CLK/2. The feedback is from CLK/2 to FBIN. Note that if an output is unused, it should be left
unconnected to improve output jitter on the active output clocks.
Absolute and One Sigma Jitter (ps)
CLK = 50M
P to P
110
CLK/2 = 25M
S1 S0 CLKIN (MHz)
Multiplier
6x
1 sigma
80
Multiplier
P to P
55
1 sigma
20
0
0
M
1
8.333
6.25
3x
4x
8x
125
90
50
20
M
M
M
1
0
3.125
4.167
2.5
16x
12x
20x
2x
130
90
8x
55
20
M
1
120
90
6x
55
20
115
90
10x
1x
55
20
0
25
130
50
55
20
1
M
1
1.5625
12.5
32x
4x
120
90
16x
2x
55
20
1
120
60
55
20
Absolute and One Sigma Jitter (ps)
CLK = 100M
P to P
100
CLK/2 = 50M
S1 S0 CLKIN (MHz)
Multiplier
6x
1 sigma
70
Multiplier
P to P
45
1 sigma
20
0
0
M
1
16.667
12.5
6.25
8.333
5
3x
4x
8x
100
70
45
20
M
M
M
1
0
16x
12x
20x
2x
110
80
8x
45
20
M
1
100
70
6x
45
20
105
70
10x
1x
40
20
0
50
90
60
40
20
1
M
1
3.125
25
32x
4x
95
70
16x
2x
45
20
1
105
70
60
20
Absolute and One Sigma Jitter (ps)
CLK = 150M
CLK/2 = 75M
S1 S0 CLKIN (MHz)
Multiplier
6x
P to P
115
120
130
130
130
115
130
110
1 sigma
70
Multiplier
P to P
50
1 sigma
20
0
0
M
1
25
18.375
9.375
12.5
7.5
3x
4x
8x
80
50
20
M
M
M
1
0
16x
12x
20x
2x
90
8x
50
20
M
1
90
6x
45
20
90
10x
1x
45
20
0
75
90
45
20
1
M
1
4.6875
37.5
32x
4x
90
16x
2x
50
20
1
70
60
20
MDS 570 H
5
Revision 010605
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS570. These ratings, which
are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of the
device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70°C
-40 to +85°C
-65 to +150°C
125°C
Ambient Operating Temperature, Commercial version
Ambient Operating Temperature, Industrial version
Storage Temperature
Junction Temperature
Soldering Temperature
260°C
Recommended Operation Conditions
Parameter
Min.
0
Typ.
Max.
70
Units
°C
Ambient Operating Temperature, Commercial version
Ambient Operating Temperature, Industrial version
Power Supply Voltage (measured in respect to GND)
-40
+85
°C
+3.15
+3.3
+3.45
V
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85°C
Parameter
Symbol Conditions
Min.
3.15
4.75
Typ.
Max.
3.45
5.25
Units
Operating Voltage
VDD
ICS570B
ICS570A
V
Operating Current
IDD
ICS570B
3.3 V, 50M input,
S1:0 = 11
16
25
mA
mA
ICS570A
5.0 V, 50M input,
S1:0 = 11
Input High Voltage
Input Low Voltage
Input High Voltage
V
ICLK, FBIN
ICLK, FBIN
S0, S1
2
V
V
V
V
IH
V
0.8
IL
IH
IM
V
VDD-0.5
Input Low Voltage
(mid-level)
V
S0, S1
VDD/2
MDS 570 H
6
Revision 010605
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Parameter
Symbol Conditions
Min.
Typ.
Max.
Units
Input Low Voltage
V
S0, S1
0.5
V
V
IL
Output High Voltage (CMOS
High)
V
I
= -4 mA
VDD-0.4
2.4
OH
OH
Output High Voltage
Output Low Voltage
Short Circuit Current
Input Capacitance
V
I
I
= -12 mA
= 12mA
V
V
OH
OH
V
0.4
OL
OS
OL
I
Each output
S0, S1
100
5
mA
pF
C
IN
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, Ambient Temperature -40 to +85°C
Parameter
Input Frequency, ICLK
Output Clock Frequency
Output to Output Skew
Output to Output Skew
Input to Output Jitter
Symbol
Conditions
FBIN from CLK/2
CLK
Min.
Typ.
Max. Units
See table on page 2
168
10
MHz
ps
ICS570B
100
100
175
200
ICS570A
ps
40 - 150 MHz
100-250
ps
ICLK to FBIN,
CLK>30MHz, Note 1
-300
-600
-1
300
600
1
ps
Input Skew, ICS570B
ICLK to FBIN,
CLK<10MHz, Note 1
ps
ns
ns
ICLK to FBIN
CLK>30MHz, Note 1
Input Skew, ICS570A
ICLK to FBIN,
-1.5
1.5
CLK<10MHz, Note 1
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle
0.8 to 2.0V, Note 2
2.0 to 0.8V, Note 2
at VDD/2
0.75
0.75
ns
ns
%
45
49 - 51
55
Note 1: Assumes clocks with same rise time, measured from rising edges at VDD/2
Note 2: Measured with 27Ω terminating resistor and 15 pF loads
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
θ
Still air
150
140
120
40
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
MDS 570 H
7
Revision 010605
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Package Outline and Package Dimensions (8-pin SOIC, 150 Mil. Body)
Package dimensions are kept current with JEDEC Publication No. 95
8
Millimeters
Inches
Min
Symbol
Min
1.35
0.10
0.33
0.19
4.80
3.80
Max
1.75
0.25
0.51
0.25
5.00
4.00
Max
.0688
.0098
.020
A
A1
B
C
D
E
e
.0532
.0040
.013
E
H
INDEX
AREA
.0075
.1890
.1497
.0098
.1968
.1574
1
2
1.27 BASIC
0.050 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
.2284
.010
.016
0°
.2440
.020
.050
8°
D
L
α
A
h x 45
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
MDS 570 H
8
Revision 010605
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS570
Multiplier and Zero Delay Buffer
Ordering Information
Part / Order Number
ICS570A
Marking
Shipping Packaging
Tubes
Package
Temperature
0 to +70° C
0 to +70° C
-40 to 85° C
-40 to 85° C
-40 to 85° C
-40 to 85° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
-40 to 85° C
-40 to 85° C
0 to +70° C
0 to +70° C
0 to +70° C
0 to +70° C
-40 to 85° C
-40 to 85° C
ICS570A
ICS570A
ICS570AI
ICS570AI
570AILF
570AILF
570ALF
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
8-pin SOIC
ICS570AT
ICS570AI
ICS570AIT
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
Tape and Reel
Tubes
ICS570AILF
ICS570AILFT
ICS570ALF
ICS570ALFT
ICS570BM
ICS570BMT
ICS570BMI
ICS570BMIT
ICS570BMLF
ICS570BMLFT
ICS570M
570ALF
ICS570B
ICS570B
ICS570BI
ICS570BI
ICS570BL
ICS570BL
ICS570M
ICS570M
ICS570MI
ICS570MI
ICS570MT
ICS570MI
ICS570MIT
Tape and Reel
“LF” denotes Pb (lead) free package.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 570 H
9
Revision 010605
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
相关型号：
SI9130DB
5- and 3.3-V Step-Down Synchronous ConvertersWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135LG-T1-E3
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9135_11
SMBus Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9136_11
Multi-Output Power-Supply ControllerWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130CG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
-
VISHAY
©2020 ICPDF网 联系我们和版权申明