ICS571M [ICSI]

Low Phase Noise Zero Delay Buffer; 低相位噪声的零延迟缓冲器


型号：	ICS571M
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	Low Phase Noise Zero Delay Buffer 低相位噪声的零延迟缓冲器逻辑集成电路光电二极管驱动
文件：	总4页 (文件大小：65K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY INFORMATION

ICS571

Low Phase Noise Zero Delay Buffer

Description

Features

• Packaged in 8 pin SOIC.

The ICS571 is a high speed, high output drive, low

phase noise Zero Delay Buffer (ZDB) which

integrates ICS’ proprietary analog/digital Phase

Locked Loop (PLL) techniques. ICS introduced

the world standard for these devices in 1992 with

the debut of the AV9170, and updated that with

the ICS570. The ICS571, part of ICS’

ClockBlocks™ family, was designed to operate at

higher frequencies, with faster rise and fall times,

and with lower phase noise. The zero delay feature

means that the rising edge of the input clock aligns

with the rising edges of both outputs, giving the

appearance of no delay through the device. There

are two outputs on the chip, one being a low-skew

divide by two of the other.

• Can function as low phase noise x2 multiplier.

• Low skew outputs. One is ÷2 of other.

• Input clock frequency up to 160 MHz at 3.3V.

• Phase noise of better than -100 dBc/Hz from

1kHz to 1MHz offset from carrier

• Can recover poor input clock duty cycle.

• Output clock duty cycle of 45/55 at 3.3V.

• High drive strength for >100 MHz outputs.

• Full CMOS clock swings with 25mA drive

capability at TTL levels.

• Advanced, low power CMOS process.

• Operating voltages of 3.0 to 5.5 V.

The chip is ideal for synchronizing outputs in a

large variety of systems, from personal computers

to data communications to video. By allowing off-

chip feedback paths, the ICS571 can eliminate the

delay through other devices. The use of dividers in

the feedback path will enable the part to multiply

by more than two.

Block Diagram

Voltage

Output

Phase

Detector,

Charge

Pump, and

Loop Filter

ICLK

FBIN

CLK

Controlled

Oscillator

Buffer

÷2

Output

Buffer

CLK/2

External feedback can come from CLK or CLK/2 (see table on page 2).

MDS 571 B

Revision 072899

Printed 11/14/00

Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

PRELIMINARY INFORMATION

ICS571

Low Phase Noise Zero Delay Buffer

Pin Assignment

ICLK

VDD

FBIN

CLK

GND

VDD

GND

CLK/2

Feedback Configuration Table and Frequency Ranges (at 3.3V)

Feedback From

CLK

CLK/2

Input Range

20 -160 MHz

10 - 80 MHz

Input clock frequency Input clock frequency/2

2xInput clock frequency Input clock frequency

CLK/2

Pin Descriptions

Number

Name

ICLK

VDD

GND

CLK/2

GND

VDD

CLK

Type Description

Reference clock input.

Connect to +3.3V or +5V. Must be same as other VDD.

Connect to ground.

Clock output per Table above. Low skew divide by two of pin 7 clock.

Connect to ground.

Connect to +3.3V or +5V. Must be same as other VDD.

Clock output per Table above.

FBIN

Feedback clock input. Connect to CLK or CLK/2 per table above.

Key: CI = clock input, I = input, O = output, P = power supply connection

External Components

The ICS571 requires a 0.01 µF decoupling capacitor to be connected between VDD and GND on each

side of the chip (between pins 2 and 3, and also between pins 6 and 5). They must be connected close to

the ICS571 to minimize lead inductance. No external power supply filtering is required for this device.

A 33 Wterminating resistor can be used next to each output pin.

MDS 571 B

Revision 072899

Printed 11/14/00

Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

PRELIMINARY INFORMATION

ICS571

Low Phase Noise Zero Delay Buffer

Electrical Specifications

Parameter

Conditions

Minimum

Typical

Maximum

Units

ABSOLUTE MAXIMUM RATINGS (Note 1)

Supply Voltage, VDD

Inputs

Referenced to GND

VDD+0.5

-0.5

Clock Output

Ambient Operating Temperature

Soldering Temperature

Storage temperature

°C

Max of 10 seconds

260

-65

150

DC CHARACTERISTICS (VDD = 5.0V or 3.3V unless otherwise noted)

Operating Voltage, VDD

5.5

Input High Voltage, VIH, ICLK, FBIN

Input Low Voltage, VIL, ICLK, FBIN

Output High Voltage, VOH, CMOS level

Output High Voltage, VOH

Pins 1, 8

VDD/2+1

VDD/2

Pins 1, 8

VDD/2-1

IOH=-4mA

IOH=-25mA

IOL=25mA

VDD-0.4

2.4

Output Low Voltage, VOL

0.4

IDD Operating Supply Current, 133 in, 133 out No Load, 3.3V

IDD Operating Supply Current, 50 in, 100 out

Short Circuit Current

No Load, 3.3V

Each Output

±100

Input Capacitance, ICLK, FBIN

AC CHARACTERISTICS (VDD = 5.0V or 3.3V unless otherwise noted)

Input Frequency, clock input

FB from CLK

160

MH z

Input Frequency, clock input

FB from CLK/2

Note 2

Skew CLK/2 with respect to CLK

Input clock to output connected to FBIN

Output Clock Rise Time, 5V

150

-500

500

850

500

Note 2

0.8 to 2.0V, 15 pF load

2.0 to 0.8V, 15 pF load

0.8 to 2.0V, 15 pF load

2.0 to 0.8V, 15 pF load

at VDD/2

0.3

0.4

Output Clock Fall Time, 5V

Output Clock Rise Time, 3.3V

Output Clock Fall Time, 3.3V

Output Clock Duty Cycle, 5V

Output Clock Duty Cycle, 3.3V

Absolute Clock Period Jitter, CLK, note 3

One Sigma Clock Period Jitter, CLK, note 3

Phase Noise, relative to carrier

0.45

0.55

52 to 55

49 to 51

±80

at VDD/2

Deviation from mean

1kHz offset

-105

-115

dBc/Hz

100kHz offset

Notes: 1. Stresses beyond these can permanently damage the device.

2. Assumes clocks with same rise time, measured from rising edges at VDD/2. Measured with 33W

termination resistors and 15 pF loads. Applies to both 3.3V and 5V operation.

3. CLK/2 has lower jitter (both absolute and one sigma, in ps) than CLK.

MDS 571 B

Revision 072899

Printed 11/14/00

Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

PRELIMINARY INFORMATION

ICS571

Low Phase Noise Zero Delay Buffer

Package Outline and Package Dimensions

8 pin SOIC

Inches

Millimeters

Min Max

0.055 0.068 1.397 1.7272

Pin 1

Symbol Min

Max

0.013 0.019 0.330

0.185 0.200 4.699

0.150 0.160 3.810

0.225 0.245 5.715

0.483

5.080

4.064

6.223

h x 45°

.050 BSC

0.015

0.016 0.035 0.406

0.004 0.01 0.102

1.27 BSC

0.381

0.889

0.254

Ordering Information

Part/Order Number

ICS571M

Marking

ICS571M

Package

8 pin SOIC

8 pin SOIC on tape and reel

Temperature

0 to 70 °C

ICS571MT

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the

infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in

normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements

are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any

ICS product for use in life support devices or critical medical instruments.

ClockBlocks is a trademark of ICS

MDS 571 B

Revision 072899

Printed 11/14/00

Integrated Circuit Systems, Inc.•525 Race Street•San Jose•CA•95126•(408)295-9800tel•(408)295-9818fax

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