ICS574 [ICSI]
Zero Delay, Low Skew Buffer; 零延迟，低偏移缓冲器
| 型号： | ICS574 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Zero Delay, Low Skew Buffer |
| 文件： | 总4页 (文件大小：58K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS574
Zero Delay, Low Skew Buffer
Description
Features
• Packaged in 8 pin narrow SOIC
The ICS574 is a low jitter, low-skew, high performance
PLL-based zero delay buffer for high speed
applications. Based on ICS’s proprietary low jitter
Phase Locked Loop (PLL) techniques, the device
provides four low skew outputs at speeds up to 160
MHz at 3.3 V. When one of the outputs is connected
directly to FBIN, the rising edge of each output is
aligned with the rising edge of the input clock. External
delay elements connected in the feedback loops will
cause the outputs to occur before the inputs by the
amount of propagation delay of the external element.
• Zero input-to-output delay
• Four 1X outputs
• Output to output skew is less than 150 ps
• Output clocks up to 160 MHz at 3.3 V
• External feedback path for output edge placement
• Spread Smart™ technology works with spread
spectrum clock generators
• Full CMOS outputs with 18 mA output drive
capability at TTL levels at 3.3 V
ICS manufactures the largest variety of clock
generators and buffers, and is the largest clock
supplier in the world.
• Advanced, low power, sub-micron CMOS process
• Operating voltage from 3.0 to 5.5 V
Block Diagram
CLK1
CLK2
CLK3
CLK4
FBIN
PLL
CLKIN
MDS 574 B
1
Revision 051801
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com
ICS574
Zero Delay, Low Skew Buffer
Pin Assignment
1
8
7
6
5
FBIN
CLKIN
2
3
4
CLK1
CLK2
GND
CLK4
CLK3
VDD
Standard 8 pin SOIC
Pin Descriptions
Number
Name
CLKIN
CLK1:4
VDD
Type Description
1
I
O
P
P
I
Clock input. Connect to input clock source.
Four clock outputs.
2, 3, 6, 7
5
4
8
Power supply. Connect both pins to same voltage (either 3.3V or 5V).
GND
Connect to ground.
Feedback input.
FBIN
Key: I = Input; O = output; P = power supply connection.
External Components
The ICS574 requires a minimum number of external components for proper operation. Decoupling capacitors of
0.1µF should be connected between VDD and GND on pins 4 and 5, as close to the device as possible. A series
termination resistor of 33 W may be used close to the pin for each clock output to reduce reflections.
MDS 574 B
2
Revision 051801
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com
ICS574
Zero Delay, Low Skew Buffer
Electrical Specifications
Parameter
Conditions
Minimum
Typical Maximum Units
ABSOLUTE MAXIMUM RATINGS (note 1)
Supply voltage, VDD
Referenced to GND
-0.5
-0.5
2000
0
7
V
Inputs and Clock Outputs
Electrostatic Discharge
Ambient Operating Temperature
Soldering Temperature
Junction temperature
Referenced to GND
MIL-STD-883
VDD+0.5
V
V
70
°C
°C
°C
°C
Max of 10 seconds
260
150
150
Storage temperature
-65
DC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)
Operating Voltage, VDD
3.00
5.50
VDD/2-1
0.4
V
V
Input High Voltage, VIH
VDD/2+1
Input Low Voltage, VIL
V
Output High Voltage, VOH
Output Low Voltage, VOL
IOH=-18 mA
IOL=18 mA
IOH=-5 mA
No Load
2.4
V
V
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD (Note 2)
VDD-0.4
V
36
±65
7
mA
mA
pF
Short Circuit Current
Input Capacitance
Each output
AC CHARACTERISTICS (VDD = 3.3 V unless specified otherwise)
Input Clock Frequency
FBIN to CLK1
FBIN to CLK1
0.8 to 2.0V
20
20
160
160
1.5
1.5
60
MHz
MHz
ns
Output Clock Frequency
Output Clock Rise Time, CL=30pF
Output Clock Fall Time, CL=30pF
Output Clock Duty Cycle, VDD=3.3V
Device to Device Skew, equally loaded
Output to Output Skew, equally loaded
Maximum Absolute Jitter
2.0 to 0.8V
ns
At 1.4V
40
50
%
rising edges at VDD/2
rising edges at VDD/2
700
150
ps
ps
150
ps
Cycle to Cycle Jitter, 30pF loads
66.67 MHz outputs
250
ps
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the
device. Prolonged exposure to levels above the operating limits but below the Absolute Maximums may
affect device reliability.
2. With CLKIN = 160 MHz, FBIN to CLK4
Using Spread Spectrum Input Clocks
The ICS574 uses ICS’ Spread Smart technology, allowing it to accurately track (pass through) any clocks that
implement spread spectrum techniques.
MDS 574 B
3
Revision 051801
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com
ICS574
Zero Delay, Low Skew Buffer
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC Publication No. 95.)
8 pin SOIC
Inches
Min Max
Millimeters
Min Max
Symbol
A
A1
B
0.0532 0.0688 1.35
0.0040 0.0098 0.10
0.0130 0.0200 0.33
0.0075 0.0098 0.19
0.1890 0.1968 4.80
0.1497 0.1574 3.80
1.75
0.24
0.51
0.24
5.00
4.00
E
H
C
D
E
INDEX
AREA
e
.050 BSC
1.27 BSC
H
h
0.2284 0.2440 5.80
0.0099 0.0195 0.25
0.0160 0.0500 0.41
6.20
0.50
1.27
h x 45°
L
D
A
A1
C
B
e
L
Ordering Information
Orderng Information
Part/Order Number
Marking
Shipping packaging
tubes
Package
8 pin SOIC
8 pin SOIC
Temperature
0-70 °C
ICS574M
ICS574M
ICS574M
ICS574MT
tape and reel
0-70 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems,
Incorporated (ICS) assumes no responsibility for either its use or for the infringement of any patents or other rights of third
parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or
other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves the
right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life
support devices or critical medical instruments.
MDS 574 B
4
Revision 051801
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126 • (408)295-9800 • www.icst.com
相关型号：
ICS574MI
PLL Based Clock Driver, 574 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8
IDT
ICS574MILF
PLL Based Clock Driver, 574 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, LEAD FREE, SOIC-8
IDT
ICS574MILFT
PLL Based Clock Driver, 574 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, LEAD FREE, SOIC-8
IDT
ICS574MIT
PLL Based Clock Driver, 574 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, SOIC-8
IDT
ICS574MLF
PLL Based Clock Driver, 574 Series, 4 True Output(s), 0 Inverted Output(s), CMOS, PDSO8, LEAD FREE, SOIC-8
IDT
ICS580M-01ILF
Low Skew Clock Driver, 580 Series, 2 True Output(s), 0 Inverted Output(s), PDSO16, 0.150 INCH, LEAD FREE, SOIC-16
IDT
©2020 ICPDF网 联系我们和版权申明