ICS580M-01 [ICSI]
Glitch-Free Clock Multiplexer; 无毛刺时钟多路复用器
| 型号： | ICS580M-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Glitch-Free Clock Multiplexer |
| 文件： | 总6页 (文件大小：64K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS580-01
Glitch-Free Clock Multiplexer
Description
Features
The ICS580-01 is a clock multiplexer (mux)
designed to switch between 2 clock sources with no
glitches or short pulses. The operation of the mux is
controlled by an input pin but the part can also be
configured to switch automatically if one of the
input clocks stops. The part also provides clock
detection by reporting when an input clock has
stopped.
• Packaged in 16 pin narrow (150 mil) SOIC
• No short pulses or glitches on output
• Operates to 200 MHz
• Does not add jitter or phase noise to the clock
• User controlled or automatic switching
• Low skew outputs
• Clock detect feature
For a clock mux with zero delay and smooth
• Ideal for systems with backup or redundant clocks
• Selectable timeouts for clock detection
• Separate supply voltages allow power supply voltage
translation
switching, see either the ICS581-01 or ICS581-02.
• Operates to 2.5 V
Block Diagram
VDDI
VDDC
CLK1
INB
1
0
OE1
INA
CLK2
SELB
OE2
Transition
Detector
NO_INA
OE3
Transition
Detector
NO_INB
OE4
Timer
DIV
MDS 580-01 A
1
Revision 030300
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
ICS580-01
Glitch-Free Clock Multiplexer
Pin Assignment
SELB
1
16 OE1
DIV
VDDI
INA
15 VDDC
14 CLK1
13 CLK2
2
3
4
5
6
7
Timeout Selection
DIV
Nominal Timeout
0
1
600 ns
75 ns
12
11
INB
NO_INA
NO_INB
GND
OE4
10 GND
OE2
9
OE3
8
Pin Descriptions
Number
Name
SELB
DIV
VDDI
INA
Type
I
I
P
I
Description
1
2
3
Mux select. Selects INB when high. Internal pull-up.
Time out select. See table above. Internal pull-up.
Supply for input clocks only. Can be higher than VDDC.
Input Clock A.
4
5
INB
I
Input Clock B.
6
7
8
9
10
11
12
13
14
15
16
GND
OE4
OE3
P
I
I
Connect to ground.
Output Enable. Tri-states NO_INB when low. Internal pull-up.
Output Enable Tri-states NO_INA when low. Internal pull-up.
Output enable. Tri-states CLK2 when low. Internal pull-up.
Connect to ground.
Goes high when clock on INB stops.
Goes high when clock on INA stops.
Clock 2 Output. Low skew compared to CLK1.
Clock 1 Output. Low skew compared to CLK2.
Main chip supply. Output clocks amplitude will match this VDD.
Output Enable. Tri-states CLK1 when low. Internal pull-up.
OE2
I
GND
NO_INB
NO_INA
CLK2
CLK1
VDDC
OE1
P
O
O
O
O
P
I
Key: I = Input; O = output; P = power supply connection
MDS 580-01 A
2
Revision 030300
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
ICS580-01
Glitch-Free Clock Multiplexer
Device Operation and Applications
The ICS580-01 consists of a glitch free mux between INA and INB controlled by SELB. The device is
designed to switch between 2 clocks, whether running or not. In the first example, clocks are running on
both INA and INB. When SELB changes, the output clock goes low after 3 cycles of the output clock
(nominally). The output then stays low for 3 cycles of the new input clock (nominally) and then starts with
the new input clock. This is shown in Figure 1.
Figure 1
INA
INB
SELB
CLK1, 2
In the second example, one of the inputs was selected and running but has since stopped (either high or low).
This is indicated by either NO_INA or NO_INB going high depending on whether INA or INB has
stopped. These signals go high following a selectable time-out period after the clock has stopped. The
timeout period is determined by the DIV input pin. The SELB pin is now changed to select the new input
clock which is running. The output clock immediately goes low and stays low for 3 cycles of the new input
clock and then starts with the new input clock. Figure 2 shows an example of this.
Figure 2
INA
INB
SELB
Timeout
NO_INA
CLK1, 2
MDS 580-01 A
3
Revision 030300
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
ICS580-01
Glitch-Free Clock Multiplexer
In the third example, the ICS580-01 is configured to automatically switch clocks when an an input stops.
The clock that could stop is connected to INA while the backup, always running, clock is connected to INB.
The output NO_INA is connected to SELB. This means that when the clock on INA stops, NO_INA
goes high selecting the clock on INB which is muxed to the output after 3 cycles. When the clock on
INA restarts, NO_INA immediately goes low, selecting the clock on INA. The output then switches in
the manner described in the first example.
The circuit diagram in Figure 3 shows a typical connection for this example. Note that CLK2 and
NO_INB are unused and so are disabled by grounding OE2 and OE4. A 33Wseries termination resistor
is used on the clock output and 2 decoupling capacitors of 0.01µF are used. All other inputs are left
floating and are therefore pulled high by the on-chip pull-ups.
Figure 3
VDD
SELB
DIV
OE1
VDDC
0.01µF
Output
Clock
VDDI
INA
CLK1
0.01µF
33W
Normal
Clock
CLK2
INB
NO_INA
Backup
Clock
GND
NO_INB
GND
OE4
OE3
OE2
Output Enable
Each output has a dedicated output enable pin. If an output is unused, it should be tri-stated by tying the
appropriate output enable pin to ground.
External Components
The ICS580-01 requires two 0.01µF decoupling capacitors, one between VDDI and GND and one between
VDDC and GND. Series termination resistors of 33Wcan be used on CLK1 and CLK2.
Split Power Supplies
The VDDI pin provides the power for the INA and INB input buffers only. All the other inputs and the
rest of the chip are connected to VDDC. This allows for supply voltage translation. For example, INA and
INB could be 5 V clocks (VDDI=5 V) and the rest of the chip could use a 3.3 V supply on VDDC giving
3.3 V output clocks. For correct operation VDDI must always be greater than or equal to VDDC.
MDS 580-01 A
4
Revision 030300
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
ICS580-01
Glitch-Free Clock Multiplexer
Electrical Specifications
Parameter
Conditions
Minimum
Typical
Maximum
Units
ABSOLUTE MAXIMUM RATINGS
Supply voltage, VDD
Referenced to GND
Referenced to GND
7
VDD+0.5
70
V
V
Inputs and Clock Outputs
Ambient Operating Temperature
Ambient Operating Temperature, I version
Soldering Temperature
-0.5
0
°C
°C
°C
°C
Industrial temperature
Max of 10 seconds
-40
85
260
Storage temperature
-65
150
DC CHARACTERISTICS (VDDC = VDDI = 3.3 V unless noted)
Operating Voltage, VDDC
2.5
VDDC
(VDDC/2)+1 VDDC/2
5.5
5.5
V
V
Operating Voltage, VDDI
Input High Voltage, VIH, note 3
Input Low Voltage, VIL, note 3
Input High Voltage, VIH
Input Low Voltage, VIL
INA and INB only
INA and INB only
Non-clock inputs
Non-clock inputs
IOH=-12mA
VDDI
V
VDDC/2 (VDDC/2)-1
V
2
VDDC
0.8
V
V
Output High Voltage, VOH
Output Low Voltage, VOL
Operating Supply Current, IDD
Short Circuit Current
VDDC-0.5
V
IOL=12mA
0.5
V
50 MHz inputs, no load
6
mA
mA
kW
pF
±70
250
4
On-chip pull-up resistor, non-clock inputs
Input Capacitance
Pull-up to VDDC
AC CHARACTERISTICS (VDDC = VDDI = 3.3 V unless noted)
Input Frequency, INA and INB. Note 1.
Propagation Delay, INA or INB to output
Transition Detector Timeout, DIV=0
Transition Detector Timeout, DIV=1
VDDC = 5 V
VDDC = 3.3 V
VDDC = 2.7 V
VDDC = 5 V
VDDC = 3.3 V
VDDC = 2.7 V
VDDI = 5 V
1/timeout
1/timeout
1/timeout
270
220
180
MH z
MH z
MH z
ns
4
5
8
10
ns
6
12
ns
175
500
750
20
350
1000
1500
40
700
2000
3000
80
ns
VDDI = 3.3 V
VDDI = 2.7 V
VDDI = 5 V
ns
ns
ns
VDDI = 3.3 V
VDDI = 2.7 V
55
110
200
210
400
1.5
ns
100
ns
Output Clock Rise Time
ns
Output Clock Fall Time
1.5
ns
Output Clock Skew, CLK1 to CLK2
Note 2
-250
0
250
ps
Note 1. Frequencies less than the minimum may cause a timeout, which will not guarantee glitch-free switching unless the clock is
actually stopped.
Note 2. Assumes identically loaded outputs with identical rise times, measured at VDD/2.
Note 3. Output duty cycle is set by duty cycle of input clock at VDDC/2.
MDS 580-01 A
5
Revision 030300
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
ICS580-01
Glitch-Free Clock Multiplexer
Package Outline and Package Dimensions
(For current dimensional specifications, see JEDEC publication no. 95.)
16 pin SOIC narrow
Inches
Symbol Min Max
0.059 0.069
0.004 0.0098 0.10
0.013 0.020 0.33
0.007 0.0098 0.19
Millimeters
Min
1.50
Max
1.75
0.25
0.51
0.25
10.00
4.00
A
A1
B
C
D
E
E
H
0.386 0.394
0.150 0.157
.050 BSC
9.80
3.80
e
1.27 BSC
5.80
H
L
0.228 0.244
6.20
1.27
0.016
0.05
0.41
D
A
A1
C
B
L
e
Ordering Information
Part/Order Number
ICS580M-01
Marking
ICS580M-01
ICS580M-01
ICS580M-01I
ICS580M-01I
Package
16 pin SOIC
16 pin SOIC on tape and reel
16 pin SOIC
16 pin SOIC on tape and reel
Temperature
0 to 70 °C
0 to 70 °C
-40 to 85°C
-40 to 85°C
ICS580M-01T
ICS580M-01I
ICS580M-01IT
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
MDS 580-01 A
6
Revision 030300
Printed 11/28/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com
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