ICS601G-01IT [ICSI]
LOW PHASE NOISE CLOCK MULTIPLIER; 低相位噪声时钟乘法器
| 型号： | ICS601G-01IT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW PHASE NOISE CLOCK MULTIPLIER |
| 文件： | 总8页 (文件大小：177K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS601-01
LOW PHASE NOISE CLOCK MULTIPLIER
Description
Features
The ICS601-01 is a low-cost, low phase noise,
• Packaged in 16-pin SOIC or TSSOP
high-performance clock synthesizer for applications
which require low phase noise and low jitter. It is ICS’
lowest phase noise multiplier, and also the lowest
CMOS part in the industry. Using ICS’ patented
analong and digital Phase-Locked Loop (PLL)
techniques, the chip accepts a 10 - 27 MHz crystal or
clock input, and produces output clocks up to 156 MHz
at 3.3 V.
• Available in Pb (lead) free package
• Uses fundamental 10 - 27 MHz crystal or clock
• Patented PLL with the lowest phase noise
• Output clocks up to 156 MHz at 3.3 V
• Low phase noise: -132 dBc/Hz at 10 kHz
• Low jitter - 18 ps one sigma typ.
• Full swing CMOS outputs with 25 mA drive capability
at TTL levels
This product is intended for clock generation. It has low
output jitter (variation in the output period), but input
and output skew and jitter are not defined nor
guaranteed. For applications which require definted
input to output timing, use the ICS670-01.
• Advanced, low power, sub-micron CMOS process
• Industrial temperature range available
• Operating voltage of 3.3V or 5V
Block Diagram
VDD
3
Reference
Divider
Phase
Comparator
Charge
Pump
Loop
Filter
CLK
VCO
X1/ICLK
X2
VCO
Divide
Crystal
Oscillator
Crystal or
clock input
REFOUT
ROM Based
Multipliers
3
4
OE
REFEN
GND
S3:0
MDS 601-01 L
1
Revision 111204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS601-01
LOW PHASE NOISE CLOCK MULTIPLIER
Pin Assignment
Multiplier Select Table
S3 S2 S1 S0 CLK (see note 2 on following page)
CLK
REFEN
VDD
1
2
3
4
5
6
7
8
GND
GND
GND
REFOUT
OE
16
15
14
13
12
11
10
9
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
TEST
TEST
Input x1
VDD
Input x3
VDD
X2
S0
Input x4
S1
S3
Input x5
X1/ICLK
S2
Input x6
Input x8
16 Pin (150 mil) TSSOP or SOIC
TEST
Crystal osc. pass through (no PLL)
Input x2
TEST
Input x8
Input x10
Input x12
Input x16
0 = connect directly to ground
1 = connect directly to VDD
Pin Descriptions
Pin
Pin
Pin
Pin Description
Number
Name
Type
1
2
CLK
Output Clock output from VCO. Output frequency equals the input frequency times multiplier.
Input Reference clock enable. Turns off the buffered crystal oscillator clock (stops low) when low.
REFEN
3
4
5
6
VDD
VDD
VDD
X2
Power Connect to +3.3V or +5V. Must match other VDDs.
Power Connect to +3.3V or +5V. Must match other VDDs.
Power Connect to +3.3V or +5V. Must match other VDDs.
XO
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal.
Leave disconnected for an external clock input.
7
8
S1
X1/ICLK
S2
Input
XI
Multiplier select pin 1. Determines CLK output per table above. Internal pull-up.
Crystal connection. Connect to a 10 - 27 MHz fundamental parallel mode crystal or clock.
Multiplier select pin 2. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 3. Determines CLK output per table above. Internal pull-up.
Multiplier select pin 0. Determines CLK output per table above. Internal pull-up.
Output Enable. Tri-states both output clocks when low. Internal pull-up.
9
Input
Input
Input
Input
10
S3
11
S0
12
OE
13
REFOUT
GND
Output Buffered crystal oscillator clock output. Controlled by REFIN.
Power Connect to ground.
14 - 16
MDS 601-01 L
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Revision 111204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS601-01
LOW PHASE NOISE CLOCK MULTIPLIER
Achieving Low Phase Noise
Figure 1 shows a typical phase noise measurement in a 125 MHz system. Therea are a few simple steps
that can be taken to achieve these levels of phase noise from the ICS601-01. Variations in VDD will
increase the hase noise, so it is important to have a stable, low noise supply voltage at the device. Use
decoupling capacitors of 0.1µF in parallel with 0.01µF. It is important to have these capacitors as close as
possible to the ICS601-01 supply pins.
Disabling the REFOUT clock is also important for achieving low phase noise; lab tests have shown that this
can reduce the phase noise by as much as 10 dBc/Hz.
0
-20
-40
-60
-80
-100
-120
-140
1.00E+01
1.00E+02
1.00E+03
1.00E+04
1.00E+05
1.00E+06
1.00E+07
Offset fromCarrier (Hz)
Figure 1. Phase Noise of ICS601-01 for 125 MHz output, 25 MHz crystal input.
VDD=3.3 V, REFOUTdisabled.
External Component/Crystal Selection
The ICS601-01 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF and 0.1µF should be connected between VDD and GND, as close to the part as
possible. A series termination resistor of 33Ω may be used for each clock output. The crystal must be
connected as close to the chip as possible. The crystal should be fundamental mode, parallel resonant. Do
not use third overtone. For exact tuning when using a crystal, capacitors should beconnected from pins X1
to ground and X2 to ground. In general, the value of these capacitors is given by the following equation,
where CL is the crystal load capacitance: Crystal caps (pF) = (CL - 5) x 2. So for a crystal with 16 pF load
capacitance, two 22 pF caps can be used. For any given board layout, ICS can measure the board
capacitance and recommend the exact capacitance value to use.
MDS 601-01 L
3
Revision 111204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS601-01
LOW PHASE NOISE CLOCK MULTIPLIER
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS601-01. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
7 V
-0.5 V to VDD+0.5 V
0 to +70 °C
-40 to +85 °C
-65 to +150 °C
125 °C
Ambient Operating Temperature, Commercial version
Ambient Operating Temperature, Industrial version
Storage Temperature
Junction Temperature
Soldering Temperature
260 °C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
-40
+3.0
+5.5
V
DC Electrical Characteristics
VDD=3.3 V 10ꢀ, Ambient temperature -40 to +85°C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
Operating Voltage
VDD
3.0
5.5
VDD/2-1
0.8
V
V
Input High Voltage
V
X1/ICLK pin only VDD/2+1
Note 1
IH
Input Low Voltage
V
X1/ICLK pin only
Note 1
V
IL
Input High Voltage
Input Low Voltage
Output High Voltage
V
2
V
V
V
IH
V
IL
V
CMOS level
VDD-0.4
2.4
OH
I
I
I
= -4mA
= -12mA
= 12mA
OH
OH
OL
Output Low Voltage
V
0.4
V
OL
MDS 601-01 L
4
Revision 111204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS601-01
LOW PHASE NOISE CLOCK MULTIPLIER
Parameter
Operating Supply Current
Short Circuit Current
Input Capacitance
Symbol
Conditions
No load, 125 MHz
Each output
Min.
Typ.
22
Max.
Units
mA
IDD
30
40
60
mA
C
OE, select pins
5
pF
IN
Note 1: Switching occurs nominally at VDD/2
AC Electrical Characteristics
VDD = 3.3V 10ꢀ, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min. Typ. Max.
Units
MHz
MHz
ns
Input Frequency
Fin
10
27
156
1.5
1.5
55
Output Frequency
Output Rise Time
Output Fall Time
at 3.3V or 5V
t
0.8 to 2.0V no load
0.8 to 2.0V, no load
at VDD/2
OR
t
ns
OF
Output Clock Duty Cycle
45
50
50
%
Maximum Absolute jitter, short
term, 125 MHz
No load
75
ps
Maximum jitter, one sigma,
125 MHz (x5)
No load
12
20
ps
Phase Noise, relative to carrier,
125 MHz (x5)
100 Hz offset
1 kHz
-90
-94
dBc/Hz
dBc/Hz
dBc/Hz
dBc/Hz
Phase Noise, relative to carrier,
125 MHz (x5)
-116
-118
-115
-120
-122
-119
Phase Noise, relative to carrier,
125 MHz (x5)
10 kHz offset
100 kHz offset
Phase Noise, relative to carrier,
125 MHz (x5)
Note 2: Input frequency limited by maximum output frequency and multiplication factor (I.e. For 16x,
maximum input frequency is 13.75 MHz).
MDS 601-01 L
5
Revision 111204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS601-01
LOW PHASE NOISE CLOCK MULTIPLIER
Package Outline and Package Dimensions (16 pin SOIC, 150 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
16
SOIC
Symbol
Min
1.35
0.10
0.33
0.19
9.80
3.80
Max
1.75
0.25
0.51
0.25
10.00
4.00
A
A1
B
C
D
E
E
H
I N
D
E X
A
A
R E
1
2
e
1.27 BASIC
H
L
α
5.80
0.40
0°
6.20
1.27
8°
D
A
A1
C
- C -
e
SEATING
PLANE
B
L
.10 (.004)
C
MDS 601-01 L
6
Revision 111204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS601-01
LOW PHASE NOISE CLOCK MULTIPLIER
Package Outline and Package Dimensions (16-pin TSSOP, 4.40 mm Body, 0.65 mm Pitch)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches
Max
16
Symbol
Min
--
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
C
D
E
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
6.40 BASIC
4.30 4.50
0.65 Basic
1 2
E1
e
L
D
0.45
0.75
0.018
0.030
α
0°
8°
0°
8°
A
2
A
A
1
c
- C -
e
SEATING
PLANE
b
L
.10 (.004)
C
MDS 601-01 L
7
Revision 111204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
ICS601-01
LOW PHASE NOISE CLOCK MULTIPLIER
Ordering Information
Part / Order Number
Marking
Shipping Packaging
Tubes
Package
Temperature
0 to 70° C
ICS601M-01
ICS601M-01T
ICS601M-01I
ICS601M-01
ICS601M-01
ICS601M-01I
ICS601M-01I
ICS601M-01LF
ICS601M-01LF
ICS601M01ILF
ICS601M01ILF
601G-01
16-pin narrow SOIC
16-pin narrow SOIC
16-pin narrow SOIC
16-pin narrow SOIC
16-pin narrow SOIC
16-pin narrow SOIC
16-pin narrow SOIC
16-pin narrow SOIC
16-pin TSSOP
Tape and Reel
Tubes
0 to 70° C
-40 to 85° C
-40 to 85° C
0 to 70° C
ICS601M-01IT
ICS601M-01LF
ICS601M-01LFT
ICS601M-01ILF
ICS601M-01ILFT
ICS601G-01
Tape and Reel
Tubes
Tape and Reel
Tubes
0 to 70° C
-40 to 85° C
-40 to 85° C
0 to 70° C
Tape and Reel
Tubes
ICS601G-01T
ICS601G-01I
601G-01
Tape and Reel
Tubes
16-pin TSSOP
0 to 70° C
601G-01I
16-pin TSSOP
-40 to 85° C
-40 to 85° C
0 to 70° C
ICS601G-01IT
ICS601G-01LF
ICS601G-01LFT
ICS601G-01ILF
ICS601G-01ILFT
601G-01I
Tape and Reel
Tubes
16-pin TSSOP
601G01LF
16-pin TSSOP
601G01LF
Tape and Reel
Tubes
16-pin TSSOP
0 to 70° C
601G01IL
16-pin TSSOP
-40 to 85° C
-40 to 85° C
601G01IL
Tape and Reel
16-pin TSSOP
“L” designates Pb (lead) free package; “I” designates industrial grade.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no
responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use. No other
circuits, patents, or licenses are implied. This product is intended for use in normal commercial applications. Any other applications such as those
requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant
any ICS product for use in life support devices or critical medical instruments.
MDS 601-01 L
8
Revision 111204
Integrated Circuit Systems ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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