ICS650-47 [ICSI]
Spread Spectrum Clock Synthesizer; 扩频时钟合成器
| 型号： | ICS650-47 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Spread Spectrum Clock Synthesizer |
| 文件： | 总10页 (文件大小：169K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-47
Spread Spectrum Clock Synthesizer
Description
Features
The ICS650-47 is a spread spectrum clock synthesizer
intended for video projector applications. It generates
an EMI optimized 50 MHz clock signal through the use
of Spread Spectrum techniques from a 25 MHz crystal
or clock input. For the 50 MHz output, the modulation
rate is 50 kHz.
• Packaged in 16-pin TSSOP (173 mil)
• Supply voltages: VDD = 3.3 V, VDDO = 2.5 V
• Peak-to-peak jitter: 125 ps typ
• Output duty cycle 45/55% (worst case)
• Guarantees +85°C operational condition
• 25 MHz crystal or reference clock input
• Zero (0) ppm frequency error on all output clocks
• Advanced, low-power CMOS process
• Industrial temperature range (0 to +85°C)
Block Diagram
VDD
VDDO
25 MHz crystal
or clock input
3
X1/CLKIN
PLL with
Spread
Spectrum
Crystal
OSC
50M
X2
External capacitors are
required with a crystal
input.
FS3:0
Control
Logic
SS_EN
2
GND
PDTS
MDS 650-47 B
1
Revision 082305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-47
Spread Spectrum Clock Synthesizer
Pin Assignment
Spread Spectrum and Output
Configuration Table
X1/CLKIN
FS0
X2
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FS3 FS2 FS1 FS0 Spread Type
SS Out
0.25
VDD
PDTS
FS2
VDD
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Center
Center
Center
Center
Center
Center
Center
Center
Down
Down
Down
Down
Down
Down
Down
Down
FS1
0.50
0.75
1.00
1.25
1.50
1.75
2.00
-0.5
SS_EN
VDD
GND
FS3
GND
VDDO
50M
NC
16-pin (173 mil) TSSOP
-0.75
-1.0
-1.25
-1.5
-1.75
-2.0
-2.25
MDS 650-47 B
2
Revision 082305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-47
Spread Spectrum Clock Synthesizer
Pin Descriptions
Pin
Number
Pin
Type
Pin Name
Pin Description
1
X1/CLKIN
Input
Crystal input. Connect this pin to a 25 MHz crystal or external input
clock.
2
3
FS0
FS1
Input
Input
Input
Select pin 0. Internal pull-up resistor. See table on page 2.
Select pin 1. Internal pull-up resistor. See table on page 2.
Spread spectrum enable pin. Internal pull-up resistor. Enabled = high.
4
SS_EN
VDD
GND
FS3
5
Power Connect to +3.3 V.
Power Connect to ground.
6
7
Input
—
Select pin 3. Internal pull-up resistor. See table on page 2.
No connect. No internal connection.
8
NC
9
50M
Output Spread Spectrum output. Weak internal pull-down when tri-stated.
Power Connect to +2.5 V.
10
11
12
13
14
VDDO
GND
VDD
FS2
Power Connect to ground.
Power Connect to +3.3 V.
Input
Input
Select pin 2. Internal pull-up resistor. See table on page 2.
PDTS
Powers down entire chip. Tri-states CLK outputs when low. Internal
pull-up.
15
16
VDD
X2
Power Connect to +3.3 V.
Output Crystal Output. Connect this pin to a 25 MHz crystal. Do not connect if
clock input is used.
External Components
Decoupling Capacitor
Crystal Load Capacitors
As with any high-performance mixed-signal IC, the
ICS650-47 must be isolated from system power supply
noise to perform optimally.
The device crystal connections should include pads for
small capacitors from X1 to ground and from X2 to
ground. These capacitors are used to adjust the stray
capacitance of the board to match the nominally
required crystal load capacitance. Because load
capacitance can only be increased in this trimming
process, it is important to keep stray capacitance to a
minimum by using very short PCB traces (and no vias)
between the crystal and device. Crystal capacitors
must be connected from each of the pins X1 and X2 to
ground.
A decoupling capacitor of 0.01µF must be connected
between each VDD and the PCB ground plane.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω.
The value (in pF) of these crystal caps should equal
(C -6 pF)*2. In this equation, C = crystal load
L
L
capacitance in pF. Example: For a crystal with a 16 pF
load capacitance, each crystal capacitor would be 20
pF [(16-6) x 2] = 20.
MDS 650-47 B
3
Revision 082305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-47
Spread Spectrum Clock Synthesizer
should not be routed next to each other with minimum
spaces, instead they should be separated and away
from other traces.
PCB Layout Recommendations
For optimum device performance and lowest output
phase noise, the following guidelines should be
observed.
3) To minimize EMI, the 33Ω series termination resistor
(if needed) should be placed close to the clock output.
1) The 0.01µF decoupling capacitors should be
mounted on the component side of the board as close
to the VDD pin as possible. No vias should be used
between the decoupling capacitors and VDD pins. The
PCB trace to VDD pins should be kept as short as
possible, as should the PCB trace to the ground via.
4) An optimum layout is one with all components on the
same side of the board, minimizing vias through other
signal layers. Other signal traces should be routed
away from the ICS650-47. This includes signal traces
just underneath the device, or on layers adjacent to the
ground plane layer used by the device.
2) The external crystal should be mounted just next to
the device with short traces. The X1 and X2 traces
Absolute Maximum Ratings
Stresses above the ratings listed below can cause permanent damage to the ICS650-47. These ratings,
which are standard values for ICS commercially rated parts, are stress ratings only. Functional operation of
the device at these or any other conditions above those indicated in the operational sections of the
specifications is not implied. Exposure to absolute maximum rating conditions for extended periods can
affect product reliability. Electrical parameters are guaranteed only over the recommended operating
temperature range.
Item
Rating
Supply Voltage, VDD
All Inputs and Outputs
5 V
-0.5 V to VDD+0.5 V
0 to +85°C
-65 to +150°C
125°C
Ambient Operating Temperature
Storage Temperature
Junction Temperature
Soldering Temperature (max. of 10 seconds)
260°C
Recommended Operation Conditions
Parameter
Min.
Typ.
Max.
+85
Units
°C
Ambient Operating Temperature
Power Supply Voltage (measured in respect to GND)
Power Supply Voltage (VDDO)
Power Supply Ramp Time, Figure 4
0
+3.135
+2.375
+3.3
+2.5
+3.465
+2.625
4
V
V
ms
MDS 650-47 B
4
Revision 082305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-47
Spread Spectrum Clock Synthesizer
DC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, VDDO = 2.5 V 5% , Ambient Temperature 0 to +85°C
Parameter
Symbol
Conditions
Min.
Typ.
Max.
Units
no load
27
mA
IDD
PDTS = 0, no load
no load
40
4
µA
mA
µA
V
Operating Supply Current
IDDO
PDTS = 0, no load
FS3:0, PDTS, SS_EN
FS3:0, PDTS, SS_EN
X1/CLKIN
1
Input High Voltage
Input Low Voltage
Input High Voltage
Input Low Voltage
Output High Voltage
Output Low Voltage
Short Circuit Current
V
2
IH
V
0.8
0.3 x VDD
0.6
V
IL
V
0.7 x VDD
1.8
V
IH
V
X1/CLKIN
V
IL
V
I
I
= -4 mA
= 4 mA
V
OH
OH
OL
V
V
OL
OS
I
50
20
mA
Ω
Nominal Output
Impedance
Z
O
Internal Pull-up Resistor
Input Leakage Current
R
FS3:0, PDTS, SS_EN
360
1
kΩ
PU
I
FS3:0, PDTS, SS_EN,
VIN=VDD
µA
I
Internal Pull-down
Resistor
R
CLK output
900
4
kΩ
PD
Input Capacitance
C
Inputs
pF
IN
MDS 650-47 B
5
Revision 082305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-47
Spread Spectrum Clock Synthesizer
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3 V 5%, VDDO = 2.5 V 5%, Ambient Temperature 0 to +85° C
Parameter
Symbol
Conditions
Min.
Typ.
25
Max. Units
MHz
Input Frequency
F
Crystal or clock input
IN
Spread Spectrum Modulation
Frequency
50
kHz
Duty Cycle
t /t
At VDD/2, Note 1 and
Figures 1 and 2
45
50
1.5
1.5
55
%
ns
ns
2 1
Output Fall Time
Output Rise Time
t
t
80% to 20%, Note 1
and Figures 1 & 3
3
4
20% to 80%, Note 1
and Figures 1 & 3
One Sigma Clock Period Jitter
Absolute Jitter, Peak-to-Peak
Note 1
30
ps
ps
t
Deviation from mean,
SS_EN=0, Note1 &
Figures 1 and 6
125
ja
Output Enable Time
Output Disable Time
t
PDTS high to PLL
locked to within 1% of
final value, Figure 5
2.5
5
ms
EN
t
PDTS low to tri-state,
Figure 5
20
6
ns
DIS
t
PLL lock-time from
power-up to 1% of final
value, Figure 4
10
ms
P
Power-up Time
Note 1: Measured with 15 pF load.
MDS 650-47 B
6
Revision 082305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-47
Spread Spectrum Clock Synthesizer
Thermal Characteristics
Parameter
Symbol
Conditions
Min.
Typ. Max. Units
Thermal Resistance Junction to
Ambient
θ
θ
θ
Still air
78
70
68
37
°C/W
°C/W
°C/W
°C/W
JA
JA
JA
JC
1 m/s air flow
3 m/s air flow
Thermal Resistance Junction to Case
θ
Marking Diagram
16
9
8
650GI47L
######
YYWW
1
Notes:
1. ###### is the lot number.
2. YYWW is the last two digits of the year and the week number that the part was assembled.
3. “L” designates Pb (lead) free package
4. Bottom marking: country of origin if not USA.
MDS 650-47 B
7
Revision 082305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-47
Spread Spectrum Clock Synthesizer
Timing Diagrams
t1
VDDs
Outputs
t2
0.01µF
CLOAD
DUT
V D D O
5 0 % of V D D O
0 V
C lo ck
GND
Figure 1: Test and Measurement Setup
Figure 2: Duty Cycle Definitions
Power Up
Time
VCO Ramp
Time
PLL Locked
t4
t3
VDD
VDDO
80% of VDDO
0V
20% of VDDO
0V
VDD
Clock
Output
0V
Figure 3: Rise and Fall Time Definitions
0 ms
4 ms
10 ms
Figure 4: Power Up and PLL Lock Timing
PDTS
1.25 V
1.25 V
1%
t DIS
t EN
VOH
CLK
Mean value
Outputs
0 V
tJA
Jitter (p - p)
Figure 6: Short Term Jitter Definition
Figure 5: PDTS to Stable Clock Output Timing
MDS 650-47 B
8
Revision 082305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-47
Spread Spectrum Clock Synthesizer
Package Outline and Package Dimensions (16-pin TSSOP, 173 Mil. Narrow Body)
Package dimensions are kept current with JEDEC Publication No. 95
Millimeters
Min Max
Inches
Max
16
Symbol
Min
--
A
A1
A2
b
--
1.20
0.15
1.05
0.30
0.20
5.1
0.047
0.006
0.041
0.012
0.05
0.80
0.19
0.09
4.90
0.002
0.032
0.007
E1
E
INDEX
AREA
C
D
E
0.0035 0.008
0.193 0.201
0.252 BASIC
0.169 0.177
0.0256 Basic
6.40 BASIC
4.30 4.50
0.65 Basic
1
2
E1
e
L
D
0.45
0°
0.75
8°
0.018
0°
0.030
8°
α
aaa
--
0.10
--
0.004
A
A2
A1
c
- C -
e
SEATING
PLANE
b
L
aaa C
Ordering Information
Part / Order Number
ICS650GI-47LF
Marking
650GI47L
650GI47L
Shipping Packaging
Tubes
Package
16-pin TSSOP
16-pin TSSOP
Temperature
0 to +85° C
ICS650GI-47LFT
Tape and Reel
0 to +85° C
Parts that are ordered with a "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS)
assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would
result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial
applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any
circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or
critical medical instruments.
MDS 650-47 B
9
Revision 082305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
P R E L I M I N A R Y I N F O R M AT I O N
ICS650-47
Spread Spectrum Clock Synthesizer
Revision History
Rev. Originator
P.Griffith
Date
Description of Change
A
8/11/05 New device.
MDS 650-47 B
10
Revision 082305
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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