ICS650R-07IT [ICSI]

Networking Clock Source; 网络时钟源


型号：	ICS650R-07IT
厂家：	INTEGRATED CIRCUIT SOLUTION INC
描述：	Networking Clock Source 网络时钟源晶体外围集成电路光电二极管时钟
文件：	总5页 (文件大小：77K)
中文：	中文翻译
下载：	下载PDF数据表文档文件

PRELIMINARY INFORMATION

ICS650-07C

Networking Clock Source

Description

Features

• Packaged in 20 pin narrow (150 mil) SSOP (QSOP)

• 12.5 MHz or 25.00 MHz fundamental crystal or

clock input

The ICS650-07C is a low cost, low jitter, high

performance clock synthesizer for networking

applications. Using analog Phase-Locked Loop

(PLL) techniques, the device accepts a 12.5 MHz

or 25.00 MHz clock or fundamental mode crystal

input to produce multiple output clocks for

networking chips, PCI devices, SDRAM, and

ASICs. The ICS650-07C outputs all have 0 ppm

synthesis error.

• Six output clocks with selectable frequencies

• SDRAM frequencies of 67, 83, 100, and 133 MHz

• Buffered crystal reference output

• Zero ppm synthesis error in all clocks

• Ideal for PMC-Sierra’s ATM switch chips

• Full CMOS output swing with 25 mA output drive

capability at TTL levels

See the MK74CB214, ICS551, and ICS552-01 for

non-PLL buffer devices which produce multiple

low-skew copies of these output clocks.

• Advanced, low power, sub-micron CMOS process

• 3.0V to 5.5V operating voltage

See the ICS570, ICS9112-16/17/18 for zero delay

buffers that can synchronize outputs and other

needed clocks.

Block Diagram

VDD

GND

Output

CLKA1

Buffer

ACS1,0

BCS1,0

Output

÷ 2

CLKA2

CLKB1

CLKB2

CLKC1

CLKC2

REFOUT

Buffer

Clock Synthesis

and Control

Circuitry

Output

Buffer

Output

Buffer

CCS

Output

Buffer

12.5 MHz or

25.00 MHz

crystal or clock

Output

Buffer

Clock

Buffer/

Crystal

Output

Buffer

Oscillator

OE (all outputs)

Optional crystal capacitors are shown and may be required for tuning of initial accuracy (determined once per board).

MDS 650-07C A

Revision 101399

Printed 11/28/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

PRELIMINARY INFORMATION

ICS650-07C

Networking Clock Source

For a 25 MHz fundamental crystal or clock input, the following four tables apply :

A Clocks Select Table (outputs in MHz)

B Clocks Select Table (outputs in MHz)

ACS1 ACS0

CLKA1

100

CLKA2

off (low)

Test

BCS1 BCS0

CLKB1

Test

CLKB2

Test

66.6667

100

33.3333

off (low)

16.6667

Test

33.3333

Test

83.3333

Test

41.6667

Test

66.6667

33.3333

133.3333

66.6667

C Clocks Select Table (outputs in MHz)

REFOUT

25 MHz

CCS

CLKC1

125

CLKC2

125

Test

0 = connect directly to GND

M = leave unconnected (automatically self biases to VDD/2)

1 = connect directly to VDD

For a 12.5 MHz crystal or clock input, the following four tables apply :

A Clocks Select Table (outputs in MHz)

B Clocks Select Table (outputs in MHz)

ACS1 ACS0

CLKA1

CLKA2

off (low)

Test

BCS1 BCS0

CLKB1

Test

CLKB2

Test

33.3333

16.6667

37.5

off (low)

8.3333

Test

16.6667

Test

41.6667

Test

20.8333

Test

33.3333

16.6667

66.6667

33.3333

C Clocks Select Table (outputs in MHz)

REFOUT

12.5 MHz

CCS

CLKC1

62.5

CLKC2

62.5

Test

37.5

0 = connect directly to GND

M = leave unconnected (automatically self biases to VDD/2)

1 = connect directly to VDD

MDS 650-07C A

Revision 101399

Printed 11/28/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

PRELIMINARY INFORMATION

ICS650-07C

Networking Clock Source

Pin Assignment

ACS0

X1/ICLK

VDD

ACS1

GND

CLKC1

CLKC2

CLKB2

BCS1

BCS0

REFOUT

CLKA1

VDD

GND

CLKA2

CLKB1 10

CCS

20 pin (150 mil) SSOP

Pin Descriptions

Number

Name

ACS0

Type Description

A Clock Select 0. Selects outputs on CLKA1 and CLKA2 per table on page 2.

Crystal connection. Connect to a crystal or leave unconnected for a clock input.

X1/ICLK

VDD

Crystal connection. Connect to a fundamental crystal or clock input.

Connect to +3.3 V or +5 V. Must be same as other VDD.

ACS1

A Clock Select 1. Selects outputs on CLKA1 and CLKA2 per table on page 2.

Connect to ground.

GND

CLKC1

CLKC2

CLKB2

CLKB1

CCS

Clock C output 1. Depends on setting of CCS per table on page 2.

Clock C output 2. Depends on setting of CCS per table on page 2. Same as CLKC1.

Clock B output 2. Depends on setting of BCS1, 0 per table on page 2.

Clock B output 1. Depends on setting of BCS1, 0 per table on page 2.

Clock C Select pin. Selects outputs on CLKC1 and CLKC2 per table on page 2.

Don't Connect. Do not connect anything to this pin.

CLKA2

GND

Clock A output 2. Depends on setting of ACS1, 0 per table on page 2.

Connect to ground.

Output Enable. Tri-states all outputs when low.

VDD

Connect to +3.3 V or +5 V. Must be same as other VDD.

CLKA1

REFOUT

BCS0

Clock A output 1. Depends on setting of ACS1, 0 per table on page 2.

Buffered Reference clock Output. Same frequency as crystal or clock input.

B Clock Select 0. Selects outputs on CLKB1 and CLKB2 per table on page 2.

B Clock Select 1. Selects outputs on CLKB1 and CLKB2 per table on page 2.

BCS1

Key: TI = tri-level input; XI, XO = crystal connections; I = Input with internal pull-up resistor;

O = Output; P = power supply connection

MDS 650-07C A

Revision 101399

Printed 11/28/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

PRELIMINARY INFORMATION

ICS650-07C

Networking Clock Source

Electrical Specifications

Parameter

Conditions

Minimum

Typical

Maximum Units

ABSOLUTE MAXIMUM RATINGS (note 1)

Supply voltage, VDD

Referenced to GND

VDD+0.5

Inputs and Clock Outputs

Ambient Operating Temperature

Ambient Operating Temperature, I version

Soldering Temperature

Referenced to GND

-0.5

°C

Industrial temp

-40

Max of 20 seconds

260

Storage temperature

-65

150

DC CHARACTERISTICS (VDD = 5.0V unless noted)

Operating Voltage, VDD

5.5

Input High Voltage, VIH, X1 pin only

Input Low Voltage, VIL, X1 pin only

Input High Voltage, VIH, all TI type inputs

Input Low Voltage, VIL, all TI type inputs

Input High Voltage, VIH, all I type inputs

Input Low Voltage, VIL, all I type inputs

Output High Voltage, VOH

Clock input

VDD/2 + 1

VDD/2

VDD/2 VDD/2 - 1

VDD-0.5

0.5

0.8

0.4

IOH=-25mA

IOL=25mA

IOH=-8mA

No Load

2.4

Output Low Voltage, VOL

Output High Voltage, VOH, CMOS level

Operating Supply Current, IDD

Short Circuit Current

VDD-0.4

Each output

ACS1, BCS1, OE

±100

200

Internal pull-up resistor

AC CHARACTERISTICS (VDD = 5.0V unless noted)

Input Frequency

12.5 or 25

1.5

MH z

Output Clock Rise Time

Output Clock Fall Time

Output Clock Duty Cycle

Frequency error

0.8 to 2.0V

2.0 to 0.8V

At VDD/2

All clocks

ppm

Absolute Jitter, short term

Variation from mean

150

Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged

exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.

External Components

The ICS650-07C requires a minimum number of external components for proper operation. Decoupling

capacitors of 0.01µF should be connected between each VDD and GND (pins 4 and 6, pins 16 and 14), as

close to the ICS650-07 as possible. A series termination resistor of 33 Wmay be used for each clock output.

The crystal must be connected as close to the chip as possible. The crystal should be a fundamental mode

(do not use third overtone), parallel resonant. Crystal capacitors should be connected from pins X1 to

ground and X2 to ground to optimize the initial accuracy. The value of these capacitors is given by the

following equation, where C is the crystal load capacitance: Crystal caps (pF) = (C -6) x 2. So for a crystal

with 16 pF load capacitance, two 20 pF caps should be used.

MDS 650-07C A

Revision 101399

Printed 11/28/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

PRELIMINARY INFORMATION

ICS650-07C

Networking Clock Source

Package Outline and Package Dimensions

(For current dimensional specifications, see JEDEC Publication No. 95.)

20 pin SSOP

Inches

Symbol Min

Millimeters

Max

Min

1.35

0.10

0.20

0.19

8.56

Max

0.053 0.069

0.004 0.010

0.008 0.012

0.007 0.010

0.337 0.344

.025 BSC

1.75

0.25

0.30

0.25

8.74

0.635 BSC

INDEX

AREA

0.228 0.244

0.150 0.157

0.016 0.050

5.79

3.81

0.41

6.20

3.99

1.27

Ordering Information

Part/Order Number

ICS650R-07

Marking

Shipping packaging

tubes

Package

Temperature

0-70°C

ICS650R-07

ICS650R-07I

20 pin SSOP

ICS650R-07T

ICS650R-07I

tape and reel

tubes

0-70°C

-40 to +85°C

ICS650R-07IT

tape and reel

Note: The C on the data sheet (ICS650-07C) is not significant when ordering this chip.

While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc (ICS) assumes no responsibility for either its use or for

the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use

in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental

requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize

or warrant any ICS product for use in life support devices or critical medical instruments.

MDS 650-07C A

Revision 101399

Printed 11/28/00

Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel • www.icst.com

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