ICS650R-12T [ICSI]

MPEG Clock Synthesizer; MPEG时钟合成器
ICS650R-12T
型号: ICS650R-12T
厂家: INTEGRATED CIRCUIT SOLUTION INC    INTEGRATED CIRCUIT SOLUTION INC
描述:

MPEG Clock Synthesizer
MPEG时钟合成器

晶体 外围集成电路 光电二极管 时钟
文件: 总4页 (文件大小:70K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
ICS650-12  
MPEG Clock Synthesizer  
Description  
Features  
The ICS650-12 is a low cost, low jitter, high  
performance clock synthesizer designed to  
produce fixed clock outputs of 13.5 MHz and  
27.0 MHz and four selectable clock outputs of two  
Processor Clocks (PCLK1 and PCLK2), Audio  
Clock (ACLK), and Communications Clock  
(CCLK). Using our patented analog Phase-  
Locked Loop (PLL) techniques, the device uses a  
27.0 MHz clock or fundamental crystal input to  
produce clocks ideal for Digital Video/MPEG-  
based applications.  
• Packaged in 20 pin tiny SSOP (QSOP)  
• Input Frequency of 27.0 MHz  
• Zero ppm synthesis error in output clocks  
• Provides fixed 13.5 MHz and 27.0 MHz.  
Also provides two selectable Processor Clocks,  
one Audio Clock, and one Communications Clock  
• Ideal for Digital Video/MPEG-based applications  
• 3.3 V or 5.0 V operating voltage  
• Entire chip powers down (when CS1=CS0=0)  
Block Diagram  
Output  
PCLK1  
Buffer  
PS2:0  
Output  
PCLK2  
Buffer  
Clock  
Synthesis  
and  
Control  
Circuitry  
Output  
Buffer  
AS2:0  
CS1:0  
ACLK  
CCLK  
Output  
Buffer  
Output  
Buffer  
13.5 MHz  
27.0 MHz  
÷ 2  
Input  
Buffer/Crystal  
Oscillator  
Output  
Buffer  
27.0 MHz  
crystal or  
clock  
MDS 650-12 A  
1
Revision 113000  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com  
ICS650-12  
MPEG Clock Synthesizer  
PCLK1 and PCLK2 Select Table (in MHz)  
Pin Assignment  
PS2 PS1 PS0  
PCLK1  
108.00  
55.00  
66.67  
80.00  
54.00  
81.00  
50.00  
60.00  
PCLK2  
54.00  
27.5  
33.33  
40.00  
27.00  
40.5  
20  
19 PS0  
18  
17 PCLK2  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
PS2  
X2  
1
2
3
4
5
6
7
PS1  
X1  
CCLK  
VDD  
CS1  
25.00  
30.00  
16  
15  
14  
13  
VDD  
AS1  
GND  
ACLK  
PCLK1  
ACLK Select Table (in MHz)  
CCLK Select Table (in MHz)  
GND  
13.5M  
AS2 AS1 AS0  
ACLK  
12.288  
11.2896  
8.192  
24.576  
8.192  
16.9344  
18.432  
11.2896  
CS1 CS0  
CCLK  
All off*  
20.00  
66.6666  
24.576  
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
1
1
0
1
0
1
8
9
12 27M  
11  
CS0  
AS2  
10  
AS0  
*Note: Entire chip powers  
down (outputs stop low)  
when CS1 = CS0 = 0.  
20 pin SSOP (QSOP)  
Pin Descriptions  
Pin #  
Name  
Type Description  
1
2
3
4, 16  
5
6, 14  
7
8
PS2  
X2  
X1  
VDD  
CS1  
GND  
ACLK  
PCLK1  
CS0  
AS2  
AS0  
27M  
13.5M  
AS1  
PCLK2  
CCLK  
PS0  
I
XO  
XI  
P
I
P
O
O
I
Processor Clock Select Pin 2. See above table.  
Crystal connection to a 27.0 MHz crystal or leave unconnected for clock input  
Crystal connection. Connect to a 27.0 MHz fundamental mode crystal or clock input.  
Connect to +3.3 V or +5.0 V.  
Communications Clock Select Pin 1. See above table.  
Connect to ground.  
Audio Clock Output. See above table.  
Processor Clock Output 1. See above table.  
Communications Clock Select 0. See above table.  
Audio Clock Select Pin 2. See above table.  
Audio Clock Select Pin 0. See above table.  
27 MHz buffered clock output.  
9
10  
11  
12  
13  
15  
17  
18  
19  
20  
I
I
O
O
I
O
O
I
13.5 MHz clock output.  
Audio Clock Select Pin 1. See above table.  
Processor Clock Output 2. See above table.  
Communications Clock Output. See above table.  
Processor Clock Select Pin 0. See above table.  
Prcoessor Clock Select Pin 1. See above table.  
PS1  
I
Key: I = Input with internal pull-up; O = output; P = power supply connection; XI, XO = crystal  
connections  
MDS 650-12 A  
2
Revision 113000  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com  
ICS650-12  
MPEG Clock Synthesizer  
Electrical Specifications  
Parameter  
Conditions  
Minimum  
Typical  
Maximum Units  
ABSOLUTE MAXIMUM RATINGS (note 1)  
Supply voltage, VDD  
Referenced to GND  
7
VDD+0.5  
70  
V
V
°C  
°C  
°C  
Inputs and Clock Outputs  
Ambient Operating Temperature  
Soldering Temperature  
Storage temperature  
Referenced to GND  
Max of 10 seconds  
-0.5  
0
260  
-65  
150  
DC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)  
Operating Voltage, VDD  
3.0  
2
5.5  
0.8  
0.4  
V
V
Input High Voltage, VIH  
Input Low Voltage, VIL  
V
Output High Voltage, VOH  
Output Low Voltage, VOL  
VDD=3.3V, IOH=-8mA  
VDD=3.3V, IOL=8mA  
2.4  
V
V
Output High Voltage, VOH, VDD = 3.3 or 5V IOH=-8mA  
VDD-0.4  
V
Operating Supply Current, IDD, at 5V  
Operating Supply Current, IDD, at 3.3V  
Short Circuit Current, VDD = 3.3 V  
Input Capacitance  
No Load  
39  
22  
±50  
7
mA  
mA  
mA  
pF  
No Load  
Each output  
Except X1  
AC CHARACTERISTICS (VDD = 3.3V or 5V unless noted)  
Input Crystal or Clock Frequency  
27  
0
MH z  
ppm  
ns  
Output Clocks Accuracy (synthesis error)  
Output Clock Rise Time  
All clocks  
1
0.8 to 2.0V  
1.5  
1.5  
60  
Output Clock Fall Time  
2.0 to 0.8V  
ns  
Output Clock Duty Cycle  
One Sigma Jitter, ACLK  
At VDD/2  
40  
50  
100  
40  
%
VDD=3.3 V  
ps  
VDD=5.0 V  
ps  
Absolute Clock Period Jitter  
VDD=3.3 V, Except CCLK=20 MHz  
VDD=5.0 V, Except CCLK=20 MHz  
±300  
±200  
ps  
ps  
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged  
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.  
External Components  
A minimum number of external components are required for proper operation. A decoupling capacitor of  
0.01 µF should be connected between VDD and GND on pins 4 and 6, and 16 and 14, and a 33 W  
terminating resistor may be used on each clock output if the trace is longer than 1 inch.  
MDS 650-12 A  
3
Revision 113000  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com  
ICS650-12  
MPEG Clock Synthesizer  
Package Outline and Package Dimensions  
(For current dimensional specifications, see JEDEC Publication No. 95.)  
20 pin SSOP  
Inches  
Symbol Min  
Millimeters  
Max  
Min  
1.35  
0.10  
0.20  
0.18  
8.55  
Max  
A
A1  
b
0.053 0.069  
0.004 0.010  
0.008 0.012  
0.007 0.010  
0.337 0.344  
.025 BSC  
1.75  
0.25  
0.30  
0.25  
8.75  
E1  
E
c
D
e
0.635 BSC  
INDEX  
AREA  
E
0.228 0.244  
0.150 0.157  
0.016 0.050  
5.80  
3.80  
0.40  
6.20  
1
2
E1  
L
4.00  
1.27  
D
A
A1  
c
b
L
e
Ordering Information  
Part/Order Number  
ICS650R-12  
Marking  
Package  
Shipping  
Tubes  
Temperature  
0 to 70 °C  
ICS650R-12  
ICS650R-12  
20 pin SSOP  
20 pin SSOP  
ICS650R-12T  
Tape and Reel 0 to 70 °C  
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its  
use or for the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is  
intended for use in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary  
environmental requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does  
not authorize or warrant any ICS product for use in life support devices or critical medical instruments.  
MDS 650-12 A  
4
Revision 113000  
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose •CA•95126• (408) 295-9800tel • www.icst.com  

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