ICS810001BK-21 [ICSI]
FEMTOCLOCKS-TM DUAL VCXO VIDEO PLL; FEMTOCLOCKS -TM双VCXO的PLL视频
| 型号： | ICS810001BK-21 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS-TM DUAL VCXO VIDEO PLL |
| 文件： | 总21页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
GENERAL DESCRIPTION
FEATURES
The ICS810001-21 is a member of the • Accepts various HD and SD references including hsync,
ICS
HiPerClockS™
HiperClockS™ family of high performance clock
solutions from ICS. The ICS810001-21 is a PLL
based synchronous clock generator that is
optimized for digital video clock jitter attenuation
transport and pixel clock rates
• Outputs HD and SD pixel rates
• One LVCMOS/LVTTL PLL clock output
• Two selectable LVCMOS/LVTTL input clocks
• LVCMOS input select lines
and frequency translation. The device contains two internal
frequency multiplication stages that are cascaded in series.
The first stage is a VCXO PLL that is optimized to provide
reference clock jitter attenuation, and to support the complex
PLL multiplication ratios needed for video rate conversion.
The second stage is a FemtoClock frequency multiplier that
provides the low jitter, high frequency video output clock.
• VCXO PLL bandwidth can be optimized for jitter attenuation
and reference tracking
• FemtoClock frequency multiplier provides low jitter, high
frequency output
• FemtoClock range: 560MHz - 700MHz
Preset multiplication ratios are selected from internal lookup
tables using device input selection pins.The multiplication ra-
tios are optimized to support most common video rates used in
professional video system applications. The VCXO requires
the use of an external, inexpensive pullable crystal. Two crys-
• RMS phase jitter @148.3516484MHz, using a
26.973027MHz crystal (12kHz - 20MHz): 0.81ps (typical)
• 3.3V supply voltage
tal connections are provided (pin selectable) so that both 60 • 0°C to 70°C ambient operating temperature
and 59.94 base frame rates can be supported. The VCXO re-
quires external passive loop filter components which are used
to set the PLL loop bandwidth and damping characteristics.
OUTPUT RATES SUPPORTED:
PIN ASSIGNMENT
Frequency (MHz)
Application
27MHz
MPEG Transport, ITU-R601, CCIR 656
26.973027MHz
74.25MHz
27MHz x 1000/1001
SMPTE 292M/60
32 31 30 29 28 27 26 25
74.17582418MHz
148.5MHz
SMPTE 292M/59.94
LF1
LF0
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
N0
SMPTE 292M/60, 1080P
SMPTE 292M/59.94, 1080P
SMPTE 259M Level “D”
N1
148.3516484MHz
36MHz
ISET
nBP1
OE
VDD
ICS810001-21
nBP0
GND
Q
GND
EXAMPLE FREQUENCY CONVERSIONS:
CLK_SEL
CLK1
VDDO
VDDA
All nine combinations from / to:
9 10 11 12 13 14 15 16
27MHz
74.175MHz
74.25MHz
NTSC or PAL hsync to 27MHz
NTSC or PAL hsync to 4xFsc
32-LeadVFQFN
5mm x 5mm x 0.95 package body
K Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
810001BK-21
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REV.A AUGUST 12, 2005
1
PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
BLOCK DIAGRAM
Loop
Filter
0
1
Phase
Detector
VCXO Input
Pre-Divider
CLK0
CLK1
0
1
VCXO
(P Value
from Table)
Charge
Pump
VCXO Feedback Divider
(M Value from Table)
CLK_SEL
VCXO
Divider
Table
4
V3:V0
VCXO Jitter Attenuation PLL
00
01
Output
Divider
FemtoClock
Frequency Multiplier
Q
01
10
11
10
11
10
11
00 = 4
01 = 8
OE
0= x22
1= x24
10 = 12
11 = 18
Master Reset
MR
MF
2
2
N1:N0
nBP1:nBP0
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REV.A AUGUST 12, 2005
2
PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Analog
Input/Output
Description
1, 2
LF1, LF0
Loop filter connection node pins.
Analog
Input/Output
3
4, 11, 25
5, 22
6, 20, 29
7
ISET
VDD
Charge pump current setting pin.
Core power supply pins.
Power
Input
Power
Input
Input
Input
nBP0,
nBP1
Pullup
PLL Bypass control pins. See block diagram.
Power supply ground.
GND
Input clock select. When HIGH selects CLK1. When LOW, selects
CLK0. LVCMOS/LVTTL interface levels.
CLK_SEL
Pulldown
8, 9
CLK1, CLK0
Pulldown Clock inputs. LVCMOS/LVTTL interface levels.
10, 14,
15, 16
V0, V1,
V2, V3
Pulldown VCXO PLL divider selection pins. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers
are reset causing the output to go low. When logic LOW, the
internal dividers and the output is enabled.
12
MR
Input
Pulldown
LVCMOS / LVTTL interface levels.
FemtoClock multiplication factor select pin.
LVCMOS/LVTTL interface levels.
13
MF
Input
Pulldown
17
18
19
VDDA
VDDO
Q
Power
Power
Output
Analog supply pin.
Output power supply pin.
VCXO PLL clock output. LVCMOS/LVTTL interface levels.
Output enable. When logic LOW, the clock output is in tristate.
21
OE
Input
Pullup
When logic HIGH, the output is enabled.
LVCMOS/LVTTL interface levels.
23, 24
26
N1, N0
Input
Input
Pulldown FemtoClock output divide select. LVCMOS/LVTTL interface levels.
Crystal select. When HIGH, selects XTAL1. When LOW, selects
Pulldown
XTAL_SEL
XTAL0. LVCMOS/LVTTL interface levels.
27,
28
XTAL_OUT1,
XTAL_IN1
Crystal oscillator interface. XTAL_IN1 is the input.
XTAL_OUT1 is the output.
Input
30,
31
XTAL_OUT0,
XTAL_IN0
Crystal oscillator interface. XTAL_IN0 is the input.
XTAL_OUT0 is the output.
Input
32
VDDX
Power
Power supply pin for VCXO charge pump.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
VDD, VDDA, VDDO = 3.465V
TBD
pF
RPULLUP
Input Pullup Resistor
51
51
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
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REV.A AUGUST 12, 2005
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PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
TABLE 3A. FIRST FREQUENCY TRANSLATION STAGE: VCXO PLL
VCXO PLL Divider Look-Up Table
Video Clock Application
Alternate Video Clock Application
V3:V0 Pins
0000
P Value
1000
1001
11000
11011
11000
4004
4004
1000
250
M Value
1000
1000
4004
4000
4000
4004
4000
1001
91
Input (kHz/MHz)
27MHz
VCXO (MHz)
27MHz
Input (kHz/MHz)
VCXO (MHz)
26.973MHz
26.973MHz
0001
27MHz
26.973MHz
27MHz
0010
74.175MHz
74.25MHz
74.25MHz
27MHz
0011
26.973MHz
27MHz
0100
0101
27MHz
26.973MHz
26.973MHz
26.973MHz
0110
27MHz
26.973MHz
27MHz
0111
26.973MHz
74.175MHz
74.25MHz
27MHz
1000
27MHz
1001
253
92
27MHz
1010
92
92
27MHz
26.973MHz
26.973MHz
45kHz
(720P/60 hsync)
33.75kHz
(1080I/60 hsync)
15.625kHz
(PAL hsync)
15.734kHz
(NTSC hsync)
28.125kHz
(1080I/50 hsync)
44.955kHz
(720P/59.94)
33.716kHz
1011
1100
1101
1110
1111
1
1
1
1
1
600
800
27MHz
27MHz
27MHz
27MHz
27MHz
26.973MHz
(1080I/59.94)
1728
1716
960
TABLE 3B. SECOND FREQUENCY TRANSLATION STAGE: FEMTOCLOCK MULTIPLIER
FemtoClock Look-Up Table
Video Clock Application
Alternate Video Clock Application
MF, N1:N0 Pins
FB Div
22
Out Div
VCXO (MHz)
27MHz
Q (MHz)
148.5MHz
74.25MHz
VCXO (MHz)
26.973MHz
26.973MHz
Q (MHz)
148.35MHz
74.175MHz
0, 00
0, 01
0, 10
0, 11
1, 00
1, 01
1, 10
1, 11
4
8
22
27MHz
22
12
18
4
22
24
24
8
24
12
18
27MHz
27MHz
54MHz
36MHz
24
TABLE 3C. BYPASS FUNCTION TABLE
Inputs
Operation
nBP1
nBP0
0
0
1
1
0
1
0
1
Bypass Frequency Translator PLL and Output Divider
Test Mode: Bypass VCXO Jitter Attenuation PLL and Frequency Translator PLL
LC Mode: Bypass VCXO Jitter Attenuation PLL
PLL Mode: Active
810001BK-21
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REV.A AUGUST 12, 2005
4
PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
810001BK-21
www.icst.com/products/hiperclocks.html
REV.A AUGUST 12, 2005
5
PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
810001BK-21
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REV.A AUGUST 12, 2005
6
PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
I
Outputs, VO
PackageThermal Impedance, θ
34.8°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = VDDX = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDA
VDDO
VDDX
IDD
Core Supply Voltage
3.135
3.135
3.135
3.135
3.3
3.3
3.3
3.3
210
10
3.465
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Charge Pump Supply Voltage
Power Supply Current
V
V
mA
mA
mA
mA
IDDA
IDDO
IDDX
Analog Supply Current
Output Supply Current
Charge Pump Supply Current
5
TBD
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = VDDX = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
Input High Voltage
Input Low Voltage
CLK0, CLK1, MR, MF,
3.0
VDD + 0.3
V
VIL
-0.3
0.8
V
P1:P0, V3:0, N1:0,
CLK_SEL, XTAL_SEL
V
DD = VIN = 3.465V
VDD = VIN = 3.465V
DD = 3.465V, VIN = 0V
150
5
µA
µA
µA
Input
High Current
IIH
OE, nBP0, nBP1
CLK0, CLK1, MR, MF,
P1:P0, V3:0, N1:0,
CLK_SEL, XTAL_SEL
V
-5
Input
Low Current
IIL
OE, nBP0, nBP1
VDD = 3.465V, VIN = 0V
-150
2.6
µA
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
V
V
0.5
NOTE 1:Outputs terminated with 50Ω toVDDO/2.
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REV.A AUGUST 12, 2005
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PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Fundamental
Frequency
14
35
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
VCXO KVCO (KVCXO); NOTE 1
Frequency Pull Range (FP); NOTE 1
Drive Level
7000
100
Hz/V
ppm
mW
1
NOTE 1: These parameters are only guaranteed when using an ICS recommended quartz crystal device.
Contact ICS regarding quartz crystal device recommendations.
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = VDDX = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
nBP0, nBP1 = 00
nBP1 = 1
Minimum Typical Maximum Units
14
31
35
MHz
MHz
FOUT
Output Frequency
175
RMS Phase Jitter, (Random),
Configuration 3 of Table 3D;
NOTE 1
148.3516484MHz,
(Integration Range: 12kHz - 20MHz)
tjit(ø)
0.81
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
450
50
ps
ꢀ
See Parameter Measurement Information section.
NOTE 1: Please refer to the Phase Noise Plot.
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REV.A AUGUST 12, 2005
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PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
TYPICAL PHASE NOISE AT 148.3516484MHZ
0
-10
-20
Fibre Channel Filter
-30
148.3516484MHz
-40
-50
-60
-70
RMS Phase Noise Jitter
12k to 20MHz = 0.81ps (typical)
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
Phase Noise Result by adding
Fibre Channel Filter to raw data
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
Phase Noise Plot
SCOPE
,
VDD
,
VDDA VDDO,
VDDX
Qx
Phase Noise Mask
LVCMOS
VEE
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-1.65V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
PHASE JITTER
VDDO
80ꢀ
tF
80ꢀ
tR
2
Q
tPW
20ꢀ
20ꢀ
Clock
Outputs
tPERIOD
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
OUTPUT RISE/FALL TIME
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PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
APPLICATION INFORMATION
EXAMPLE LOOP FILTER COMPONENT VALUES FOR VARIOUS VCXO DIVIDER SELECTIONS
VCXO PLL Divider
Loop Filter Component Selection
VCXO PLL Performance
Loop Filter
Example
Number
Selection
Rset
(kΩ)
Iset
(µA)
Rs
(kΩ)
Cs
(µF)
Cp
(pF)
VCXO PLL
Loop BW (Hz/-3dB)
FB Divider (MValue)
Damping Factor
2.2
4.4
4.4
2.2
2.2
2.2
4.4
500
250
250
500
500
500
250
261
261
53.6
499
261
105
23.2
0.033
0.068
1.5
1500
3300
200
100
20
1.4
1.4
1.4
1.3
1.5
1.6
1.6
1.8
1.6
1.5
1.4
1
1
2
3
4
5
6
7
1000, 1001
4000, 4001
68000
1500
0.033
0.15
1
100
50
6800
33000
33000
20
91, 92
600
1
100
170
125
105
100
58
800
960
4.4
2.2
250
500
261
0.068
0.01
2200
470
8
9
1000, 1000
1726, 1728
4000, 4004
1726, 1728
27
0.7
1.5
1000
100
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PRELIMINARY
ICS810001-21
Integrated
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Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
APPLICATION EXAMPLE 1: 27MHZ TO 74.25MHZ
Cs = 0.068
Rs = 261 k
F
VCXO PLL Loop Characteristics with this configuration:
- Bandwidth (-3dB) = 100 Hz
- Damping Factor = 1.4
Cp = 3300 pf
RSET = 4.4k
(Makes ISET = 250 A)
0
1
Phase
Detector
VCXO Input
Pre-Divider
CLK0 = 27 MHz
CLK1 = GND
CLK_SEL = 0
0
1
VCXO
Charge
Pump
= 1000
VCXO Feedback Divider
= 1000
VCXO
Divider
Table
4
V3:V0 = 0000
VCXO Jitter Attenuation PLL
00
01
Output
Divider
FemtoClock
Frequency Multiplier
Q = 74.25 MHz
OE = 1
01
10
11
10
11
10
11
00 = 4
01 = 8
= x 22
10 = 12
11 = 18
Master Reset
MR = 0
MF = 0
2
2
N1:N0 = 01
nBP1:nBP0 = 11
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PRELIMINARY
ICS810001-21
Integrated
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Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
APPLICATION EXAMPLE 2: 27MHZ TO 74.175MHZ
VCXO PLL Loop Characteristics with this configuration:
Cs = 0.068
Rs = 261 k
F
- Bandwidth (-3dB) = 100 Hz
- Damping Factor = 1.4
Cp = 3300 pf
RSET = 4.4k
(Makes ISET = 250 A)
0
1
Phase
Detector
VCXO Input
Pre-Divider
CLK0 = 27 MHz
CLK1 = GND
CLK_SEL = 0
0
1
VCXO
Charge
Pump
= 1001
VCXO Feedback Divider
= 1000
VCXO
Divider
Table
4
V3:V0 = 0001
VCXO Jitter Attenuation PLL
00
01
Output
Divider
FemtoClock
Frequency Multiplier
Q = 74.125 MHz
OE = 1
01
10
11
10
11
10
11
00 = 4
01 = 8
= x 22
10 = 12
11 = 18
Master Reset
MR = 0
MF = 0
2
N1:N0 = 01
2
nBP1:nBP0 = 11
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PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
DESCRIPTION OF THE PLL STAGES
SETTING THE VCXO PLL LOOP RESPONSE
The ICS843002-21 is a two stage device, a VCXO PLL fol- TheVCXO PLL loop response is determined both by fixed device
lowed by a low phase noise FemtoClock frequency multiplier. characteristics and by other characterizes set by the user.This
The VCXO uses an external pullable crystal which can be includes the values of RS, CS, CP and RSET as shown in the
pulled 100ppm by the VCXO PLL circuitry to phase lock it to ExternalVCXO PLL Components figure on this page.
the input reference frequency. There are two VCXO crystal
ports in order to provideVCXO frequency versatility.For HDTV The VCXO PLL loop bandwidth is approximated by:
applications, this allows the use of a 26.973027MHz crystal
RS x ICP x KO
for the generation of 74.175MHz, or a 27.00MHz crystal for
the generation of 74.25MHz, for example.
NBW (VCXO PLL) =
2π x Feedback Divider
The VCXO output frequency can be output directly from the WHERE:
device, or it can be passed to the FemtoClock frequency
multiplier which will multiply it up to a higher frequency.
RS = Value of resistor RS in loop filter in Ohms
ICP = Charge pump current in amps (see table on page 12)
KO = VCXO Gain in Hz/V
Feedback Divider = 1 to 11011 (as determined by inputs
V3:V0)
VCXO PLL LOOP RESPONSE CONSIDERATIONS
Loop response characteristics of the VCXO PLL is affected
by the VCXO feedback divider value (bandwidth and damping
factor), and by the external loop filter components (bandwidth,
damping factor, and 2nd frequency response).A practical range
of VCXO PLL bandwidth is from about 1Hz to about 1kHz.
The setting of VCXO PLL bandwidth and damping factor is
covered later in this document. A PC based PLL bandwidth
calculator is also under development. For assistance with loop
bandwidth suggestions or value calculation, please contact
ICS applications.
The above equation calculates the “normalized” loop bandwidth
(denoted as “NBW”) which is approximately equal to the - 3dB
bandwidth. NBW does not take into account the effects of
damping factor or the second pole imposed by CP. It does,
however, provide a useful approximation of filter performance.
To prevent jitter on the clock output due to modulation of the
VCXO PLL by the phase detector frequency, the following general
rule should be observed:
Table 3A shows frequency translation configuration examples.
Note that in the first two V3:V0 selections the VCXO PLL feed-
back divider is the same value of 1000.This means the VCXO
PLL loop response (bandwidth and damping factor) will be the
same for all of these settings.
ƒ (Phase Detector)
NBW (VCXO PLL) ≤
20
ƒ(Phase Detector) = Input Frequency ÷ Pre-Divider)
The PLL loop damping factor is determined by:
The same is true for V3:V0 = 0010 through 0110.This means
the device can be configured to translate between 74.175MHz,
74.25MHz, and 27MHz (from any one to another, all nine com-
binations) and it will maintain the same loop response char-
acteristics. This is also true for V3:V0 = 1000 through 1010.
RS
2
ICP x CS x KO
DF = x
Feedback Divider
For high VCXO PLL feedback divider values, the phase de-
tector rate, and therefore loop filter charge pulse rate, is greatly
reduced.To prevent output clock wander, low leakage capaci-
tors should be used. In addition, when loop bandwidth is low
(say below 20Hz), capacitors with low microphonic sensitiv-
ity should be used. PPS film type capacitors are one type that
perform well in this environment. Below 5Hz, shielding should
be considered to prevent excessive phase wander (low fre-
quency phase jitter or clock phase deviation).
WHERE:
CS = Value of capacitor CS in loop filter in Farads
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FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
EXTERNAL VCXO PLL COMPONENTS
In general, the loop damping factor should be 0.7 or greater to The best way to set the value of CP is to use the filter response
ensure output stability. A higher damping factor will create less software available from ICS (please refer to the following section).
CP should be increased in value until it just starts affecting the
peaking in the passband. A higher damping factor may also
increase lock time and output clock jitter when there is excess passband peak.
digital noise in the system application, due to the reduced ability
of the PLL to respond to and therefore compensate for phase
noise ingress.
NOTES ON EXTERNAL CRYSTAL LOAD CAPACITORS
In the loop filter schematic diagram, capacitors are shown be-
tween pins 27/30 to ground and between pins 38/31 to ground.
These are optional crystal load capacitors which can be used to
center tune the external pullable crystal (the crystal frequency
can only be lowered by adding capacitance, it cannot be raised).
Note that the addition of external load capacitors will decrease
the crystal pull range and the Kvco value.
64
1
27/30
28/31
LF1
LF0
2
3
RS
CS
LOOP FILTER RESPONSE SOFTWARE
ISET
CP
Online tools to calculate loop filter response can be found at
www.icst.com. Contact your local sales representative if a tool
cannot be found for this product.
RSET
The external crystal devices and loop filter components should
be kept close to the device. Loop filter and crystal PCB
connection traces should be kept short and well separated from
each other and from other signal traces. Other signal traces
shouldnot run underneath the device, the loop filter or crystal
components.
NOTES ON SETTING THE VALUE OF CP
As another general rule, the following relationship should be
maintained between components CS and CP in the loop filter:
CS
CP =
20
CP establishes a second pole in the VCXO PLL loop filter. For
higher damping factors (> 1), calculate the value of CP based on
a CS value that would be used for a damping factor of 1.This will
minimize baseband peaking and loop instability that can lead to
output jitter.
CP also dampens VCXO PLL input voltage modulation by the
charge pump correction pulses. A CP value that is too low will
result in increased output phase noise at the phase detector
frequency due to this. In extreme cases where input jitter is high,
charge pump current is high, and CP is too small, theVCXO PLL
input voltage can hit the supply or ground rail resulting in non-
linear loop response.
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PRELIMINARY
ICS810001-21
Integrated
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FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
VCXO CRYSTAL SELECTION
Choosing a crystal with the correct characteristics is one of the accuracy of a VCXO. Below are the key variables and an
most critical steps in using aVoltage Controlled Crystal Oscillator example of using the crystal parameters to calculate the tuning
(VCXO). The crystal parameters affect the tuning range and range of the VCXO.
VC
Oscillator
“Control Voltage”
CV
CV
VCXO (Internal)
XTAL
CS1
CS2
CL1
CL2
Optional
FIGURE 1: VCXO OSCILLATOR CIRCUIT EXAMPLE
CL1, CL2 Load tuning capacitance used for fine tuning or
centering nominal frequency
VC Control voltage used to tune frequency
CV Varactor capacitance, varies due to the change in
control voltage
CS1, CS2 Stray Capacitance caused by pads, vias, and other
board parasitics
CRYSTAL PARAMETER EXAMPLES
Symbol Parameter
Minimum Typical Maximum Units
fN
fT
fS
Nominal Frequency
19.44
MHz
Frequency Tolerance
Frequency Stability
Operating Temperature Range
Load Capacitance
Shunt Capacitance
Pullability Ratio
20
20
ppm
ppm
°C
0
70
CL
12
4
pF
CO
pF
C0/C1
ESR
220
240
20
1
Equivalent Series Resistance
Drive Level
mW
ppm
Aging @ 25°C
3 per year
Mode of Operation
Fundemental
VARACTOR PARAMETERS
Symbol Parameter
Test Condition Typical Unit
CV LOW
CV HIGH
Low Varactor Capacitance
High Varactor Capacitance
VC = 0V
15.4
29.6
pF
pF
VC = 3.3V
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FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
FORMULAS
(CL1 + CS1 + CV_LOW) · (CL2 + CS2 + CV_LOW
)
(CL1 + CS1 + CV_HIGH · (CL2 + CS2 + CV_HIGH
)
CLOW
=
CHIGH
=
(CL1 + CS1 + CV_LOW) + (CL2 + CS2 + CV_LOW
)
(CL1 + CS1 + CV_HIGH) + (CL2 + CS2 + CV_HIGH
)
CLow is the effective capacitance due to the low varactor
capacitance, load capacitance and stray capacitance.
CHigh is the effective capacitance due to the high varactor
capacitance, load capacitance and stray capacitance.
CHigh determines the low frequency component on the
TPR (Total Pull Range).
C
Low determines the high frequency component on the
TPR (Total Pull Range).
1
1
TPR =
–
· 106
(
)
2 · C0/C1 · (1+CLOW /C0)
2 · C0/C1 · (1+CHIGH/C0)
AbsolutePullRange (APR) =TotalPullRange – (FrequencyTolerance + FrequencyStability + Aging)
EXAMPLE CALCULATIONS
Using the tables and figures above, we can now calculate the the inaccuracy due to aging is 15ppm. Third, though many
TPR and APR of the VCXO using the example crystal boards will not require load tuning capacitors (CL1, CL2), it is
parameters. For the numerical example below there were some recommended for long-term consistent performance of the
assumptions made. First, the stray capacitance (CS1, CS2), which system that two tuning capacitor pads be placed into every
is all the excess capacitance due to board parasitic, is 4pF. design. Typical values for the load tuning capacitors will range
Second, the expected lifetime of the project is 5 years; hence from 0 to 4pF.
(0 + 4pF + 15.4pF) · (0 + 4pF + 15.4pF)
(0 + 4pF + 15.4pF) + (0 + 4pF + 15.4pF)
(0 + 4pF + 29.6pF) · (0 + 4pF + 29.6pF)
(0 + 4pF + 29.6pF) + (0 + 4pF + 29.6pF)
= 9.7pF
= 16.8pF
CLOW
=
CHIGH =
1
1
TPR =
–
· 106 = 226.5ppm
(
)
2 · 220 · (1+9.7pF/4pF)
2 · 220 · (1+16.8pF/4pF)
TPR = 113.25ppm
APR = 113.25ppm – (20ppm + 20ppm + 15ppm) = 58.25ppm
The example above will ensure a total pull range of 113.25 (C0/C1 ratio) can be used. Also, with the equations above, one
ppm with an APR of 58.25ppm. Many times, board designers can vary the frequency tolerance, temperature stability, and
may select their own crystal based on their application. If the aging or shunt capacitance to achieve the required pullability.
application requires a tighter APR, a crystal with better pullability
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PRELIMINARY
ICS810001-21
Integrated
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Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
NOTES ON SETTING CHARGE PUMP CURRENT
The recommended range for the charge pump current is 50μA
to 300μA. Below 50μA, loop filter charge leakage, due to PCB or
capacitor leakage, can become a problem.This loop filter leakage
can cause locking problems, output clock cycle slips, or low
frequency phase noise.
As can be seen in the loop bandwidth and damping factor
equations or by using the filter response software available from
ICS, increasing charge pump current (ICP) increases both
bandwidth and damping factor.
CHARGE PUMP CURRENT, EXAMPLE SETTINGS
RSET
17.6k
8.8k
4.4k
2.2k
Charge Pump Current (ICP)
62.5µA
125µA
250µA
500µA
1E-3
100E-6
10E-6
1k
10k
100k
RSET, Ω
FIGURE 2. CHARGE PUMP CURRENT VS. VALUE OF RSET (EXTERNAL RESISTOR) GRAPH
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS810001-21 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, VDDx, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 3 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin.
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 3. POWER SUPPLY FILTERING
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PRELIMINARY
ICS810001-21
Integrated
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FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN
θJA vs. 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8°C/W
TRANSISTOR COUNT
The transistor count for ICS810001-21 is: 9365
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PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
VHHD-2
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
0.80
0
1.00
0.05
A1
A3
b
--
0.25 Ref.
0.25
0.18
0.30
8
ND
NE
D
8
5.00 BASIC
2.25
D2
E
1.25
1.25
0.30
3.25
3.25
0.50
5.00 BASIC
2.25
E2
e
0.50 BASIC
0.40
L
Reference Document: JEDEC Publication 95, MO-220
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PRELIMINARY
ICS810001-21
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ D UAL VCXO VIDEO PLL
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS810001BK-21
ICS810001BK-21T
Marking
Package
Shipping Packaging
tray
Temperature
0°C to 70°C
0°C to 70°C
ICS10001B21
ICS10001B21
32 Lead VFQFN
32 Lead VFQFN
2500 tape & reel
The aforementioned trademarks, HiPerClockS™ and FEMTOCLOCKS™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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REV.A AUGUST 12, 2005
21
相关型号：
ICS810252AKI-03LFT
Clock Generator, 156.25MHz, 5 X 5 MM, 0.925 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32
IDT
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