ICS81006AKT [ICSI]
VCXO-TO-6 LVCMOS OUTPUTS; VCXO - TO- 6 LVCMOS输出
| 型号： | ICS81006AKT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | VCXO-TO-6 LVCMOS OUTPUTS |
| 文件： | 总14页 (文件大小：163K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
GENERAL DESCRIPTION
FEATURES
The ICS81006 is a high performance, low • Six LVCMOS/LVTTL outputs, 20Ω nominal
ICS
jitter/low phase noise VCXO and is a
member of the HiPerClockS™ family of high
performance clock solutions from ICS. The
ICS81006 works in conjunction with a
output impedance
HiPerClockS™
• Output Q5 can be selected for ÷1 or ÷2 frequency relative
to the crystal frequency
pullable crystal to generate an output clock over the
range of 12MHz - 40MHz and has 6 LVCMOS outputs,
effectively integrating a fanout buffer function.
• Output frequency range: 12MHz to 40MHz
• Crystal pull range:
ꢀ0ppm ꢁtypicalꢂ
• Synchronous output enable places outputs in High-Z state
• On-chip filter onVIN to suppress noise modulation of VCXO
• VDD/VDDO combinations
The frequency of the VCXO is adjusted by the VC control
voltage input. The output range is 100ppm around the
nominal crystal frequency. The VC control voltage range
is 0 - VDD. The device is packaged in a small 4mm x 4mm
VFQFN package and is ideal for use on space
constrained boards typically encountered in ADSL/
VDSL applications.
3.3V/3.3V
3.3V/2.5V
3.3V/1.8V
2.5V/2.5V
2.5V/1.8V
• 4mm x 4mm 20 Lead VFQFN package is ideal for space
constrained designs
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
ꢁPullupꢂ
OE0
SYNC
Q0
Q1
Q2
20 1ꢀ 18 17 16
15 GND
VC
LP Filter
XTAL_IN
1
2
3
4
5
XTAL_OUT
14 Q2
13
VDD
VC
VDDO
XTAL_IN
12 Q3
VCXO
DIV_SEL_Q5
11 GND
6
7
8
ꢀ
10
XTAL_OUT
Q3
Q4
ICS81006
20-LeadVFQFN
4mm x 4mm x 0.ꢀ5 package body
K Package
TopView
0: ÷1
1: ÷2
Q5
ꢁPulldownꢂ
DIV_SEL_Q5
ꢁPullupꢂ
OE1
SYNC
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ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
XTAL_IN,
XTAL_OUT
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
1, 2
Input
3
4
VDD
VC
Power
Input
Core supply pin.
Control voltage input.
Output divider select pin for Q5 output. When LOW, ÷1. When HIGH,
÷2, LVCMOS/LVTTL interface levels.
5
DIV_SEL_Q5 Input Pulldown
Output enable pin. When HIGH, Q5 output is enabled.
When LOW, forces Q5 to HiZ state. LVCMOS/LVTTL interface levels.
6
OE1
Input
Power
Output
Power
Input
Pullup
7, 11, 15, 1ꢀ
GND
Power supply ground.
8, 10, 12,
14, 16, 18
Q5, Q4, Q3,
Q2, Q1, Q0
Single-ended clock outputs. LVCMOS/LVTTL interface levels.
15Ω typical output impedance.
Output supply pins.
ꢀ, 13, 17
VDDO
Output enable pin. When HIGH, Q0:Q4 outputs are enabled. When
LOW, forces Q0:Q4 to HiZ state. LVCMOS/LVTTL interface levels.
20
OE0
Pullup
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical Maximum Units
CIN
Input Capacitance OE0, OE1
4
pF
pF
V
DD = VDDO = 3.465V
3
4
V
DD = 3.465V or 2.625V,
pF
pF
CPD
Power Dissipation Capacitance
V
DDO = 2.625V
VDD = 3.465V or 2.625V,
DDO = 2V
6
V
RPULLUP
Input Pullup Resistor
51
51
kΩ
kΩ
Ω
RPULLDOWN
Input Pulldown Resistor
V
DDO = 3.3V
20
25
38
ROUT
Output Impedance
VDDO = 2.5V
VDDO = 1.8V
Ω
Ω
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ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
38.5°C/W ꢁ0 mpsꢂ
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢃ, VDDO = 3.3V 5ꢃ = 2.5V 5ꢃ= 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
Core Supply Voltage
3.135
3.135
2.375
1.6
3.3
3.3
2.5
1.8
3.465
3.465
2.625
2.0
V
V
VDDO
Output Supply Voltage
V
V
IDD
Power Supply Current
Output Supply Current
50
mA
mA
IDDO
20
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5ꢃ, VDDO = 2.5V 5ꢃ= 1.8V 0.2V,TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
Core Supply Voltage
2.375
2.375
1.6
2.5
2.5
1.8
2.625
2.625
2.0
V
V
VDDO
Output Supply Voltage
V
IDD
Power Supply Current
Output Supply Current
50
mA
mA
IDDO
20
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, TA = 0°C TO 85°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
V
V
V
V
DD = 3.3V 5ꢃ
DD = 2.5V 5ꢃ
DD = 3.3V 5ꢃ
DD = 2.5V 5ꢃ
2
VDD + 0.3
VDD + 0.3
0.8
V
V
VIH
Input High Voltage
1.7
-0.3
-0.3
0
V
OE0, OE1,
DIV_SEL_Q5
VIL
VC
IIH
Input Low Voltage
0.7
V
VCXO Control Voltage
VDD
V
DIV_SEL_Q5
V
V
V
V
DD = 3.3V or 2.5V 5ꢃ
DD = 3.3V or 2.5V 5ꢃ
DD = 3.3V or 2.5V 5ꢃ
DD = 3.3V or 2.5V 5ꢃ
150
µA
µA
µA
µA
µA
V
Input High Current
Input Low Current
OE0, OE1
DIV_SEL_Q5
OE0, OE1
5
-5
IIL
II
-150
-100
2.6
Input Current of VC pin
VDD = 3.465V or 2.625V
VDDO = 3.3V 5ꢃ
100
VOH
Output High Voltage;NOTE 1
V
DDO = 2.5V 5ꢃ
DDO = 1.8V 0.2V
DDO = 3.3V or 2.5V 5ꢃ
DDO = 1.8V 0.2V
1.8
V
V
1.5
V
V
0.5
0.4
V
VOL
Output Low Voltage;NOTE 1
V
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
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ICS81006
Integrated
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VCXO-TO-6 LVCMOS OUTPUTS
TABLE 4A. AC CHARACTERISTICS, VDD =VDDO = 3.3V 5ꢃ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
12
1ꢀ.44
40
MHz
RMS Phase Jitter ꢁRandomꢂ;
NOTE 1
tjitꢁØꢂ
Integration Range: 1kHz- 1MHz
0.35
ps
Q0:Q4
Q0:Q5
30
100
700
56
ps
ps
ps
ꢃ
Output Skew;
NOTE 2, 3
tskꢁoꢂ
DIV_SEL_Q5 = ÷1
20ꢃ to 80ꢃ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
44
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V 5ꢃ, VDDO = 2.5V 5ꢃ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
12
1ꢀ.44
40
MHz
RMS Phase Jitter ꢁRandomꢂ;
NOTE 1
tjitꢁØꢂ
Integration Range: 1kHz- 1MHz
0.38
ps
Q0:Q4
Q0:Q5
20
ꢀ0
ps
ps
ps
ꢃ
Output Skew;
NOTE 2, 3
tskꢁoꢂ
DIV_SEL_Q5 = ÷1
20ꢃ to 80ꢃ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
300
45
800
55
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4C. AC CHARACTERISTICS, VDD = 3.3V 5ꢃ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
12
1ꢀ.44
40
MHz
RMS Phase Jitter ꢁRandomꢂ;
NOTE 1
tjitꢁØꢂ
Integration Range: 1kHz-1MHz
0.27
ps
Q0:Q4
Q0:Q5
46
175
1400
56
ps
ps
ps
ꢃ
Output Skew;
NOTE 2, 3
tskꢁoꢂ
DIV_SEL_Q5 = ÷1
20ꢃ to 80ꢃ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
450
44
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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ICS81006
Integrated
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VCXO-TO-6 LVCMOS OUTPUTS
TABLE 4D. AC CHARACTERISTICS, VDD =VDDO = 2.5V 5ꢃ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
12
1ꢀ.44
40
MHz
RMS Phase Jitter ꢁRandomꢂ;
NOTE 1
tjitꢁØꢂ
Integration Range: 1kHz-1MHz
0.28
ps
Q0:Q4
Q0:Q5
25
100
800
55
ps
ps
ps
ꢃ
Output Skew;
NOTE 2, 3
tskꢁoꢂ
DIV_SEL_Q5 = ÷1
20ꢃ to 80ꢃ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
300
45
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4E. AC CHARACTERISTICS, VDD = 2.5V 5ꢃ, VDDO = 1.8V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
12
1ꢀ.44
40
MHz
RMS Phase Jitter ꢁRandomꢂ;
NOTE 1
tjitꢁØꢂ
Integration Range: 1kHz-1MHz
0.26
ps
Q0:Q4
Q0:Q5
40
175
1400
60
ps
ps
ps
ꢃ
Output Skew;
NOTE 2, 3
tskꢁoꢂ
DIV_SEL_Q5 = ÷1
20ꢃ to 80ꢃ
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
450
40
NOTE 1: Please refer to the Phase Noise Plot.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
TYPICAL PHASE NOISE AT 19.44MHZ @ 3.3V CORE/3.3V OUTPUT
0
-10
-20
19.44MHz
RMS Phase Jitter ꢁRandomꢂ
1kHz to 1MHz = 0.35ps ꢁtypicalꢂ
-30
-40
-50
-60
-70
-80
-ꢀ0
-100
-110
-120
-130
-140
-150
-160
-170
-180
-1ꢀ0
100
1k
10k
OFFSET FREQUENCY (HZ)
100k
1M
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ICS81006
Integrated
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VCXO-TO-6 LVCMOS OUTPUTS
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢃ
2.05V 5ꢃ 1.25V 5ꢃ
SCOPE
SCOPE
VDD,
VDDO
VDD
VDDO
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V 5ꢃ
-1.25V 5ꢃ
3.3V CORE/3.3V OUTPUT LOAD ACTEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD ACTEST CIRCUIT
1.25V 5ꢃ
2.4V 0.065V 0.ꢀV 0.1V
SCOPE
SCOPE
VDD
VDD,
VDDO
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.25V 5ꢃ
-0.ꢀV 0.1V
3.3V CORE/1.8V OUTPUT LOAD ACTEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD ACTEST CIRCUIT
1.6V 0.025V
0.ꢀV 0.1V
Phase Noise Plot
SCOPE
VDD
Phase Noise Mask
VDDO
Qx
LVCMOS
GND
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
-0.ꢀV 0.1V
2.5 CORE/1.8V OUTPUT LOAD ACTEST CIRCUIT
RMS PHASE JITTER
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ICS81006
Integrated
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VCXO-TO-6 LVCMOS OUTPUTS
VDD
VDDO
2
Qx
Qy
2
Q0:Q5
tPW
tPERIOD
VDDO
2
tskꢁoꢂ
tPW
x 100ꢃ
odc =
tPERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80ꢃ
tF
80ꢃ
20ꢃ
20ꢃ
Clock
Outputs
tR
OUTPUT RISE/FALL TIME
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ICS81006
Integrated
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VCXO-TO-6 LVCMOS OUTPUTS
APPLICATION INFORMATION
VCXO CRYSTAL SELECTION
Choosing a crystal with the correct characteristics is one of range and accuracy of a VCXO. Below are the key variables
the most critical steps in using a Voltage Controlled Crystal and an example of using the crystal parameters to calculate
Oscillator ꢁVCXOꢂ. The crystal parameters affect the tuning the tuning range of the VCXO.
VC
Oscillator
➤
Control Voltage
CV
CV
VCXO ꢁInternalꢂ
XTAL
CS1
CS2
CL1
CL2
Optional
FIGURE 1: VCXO OSCILLATOR CIRCUIT
CL1, CL2 Load tuning capacitance used for fine tuning or
centering nominal frequency
VC Control voltage used to tune frequency
CV Varactor capacitance, varies due to the change in
control voltage
CS1, CS2 Stray Capacitance caused by pads, vias, and other
board parasitics
TABLE 5. EXAMPLE CRYSTAL PARAMETERS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fN
fT
fS
Nominal Frequency
Frequency Tolerance
Frequency Stability
Operating Temperature Range
Load Capacitance
Shunt Capacitance
Pullability Ratio
1ꢀ.44
MHz
ppm
ppm
°C
20
20
0
70
CL
12
4
pF
CO
pF
C0, C1
ESR
220
240
20
1
Equivalent Series Resistance
Drive Level
mW
ppm
Aging @ 25°C
3 per year
Mode of Operation
Fundamental
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ICS81006
Integrated
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Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
TABLE 6. VARACTOR PARAMETERS
Symbol Parameter
Test Conditions
VC = 0V
Minimum Typical Maximum Units
CV_LOW
CV_HIGH
Low Varactor Capacitance
High Varactor Capacitance
15.4
2ꢀ.6
pF
pF
VC = 3.3V
FORMULAS
CL1 + CS1 + CV _ High
⋅
+
CL2 + CS 2 + CV _ High
CL1 + CS1 + CV _ Low
⋅
+
CL2 + CS 2 + CV _ Low
CHigh
=
CLow
=
(
CL1 + CS1 + CV _ High
)
(
CL2 + CS 2 + CV _ High
)
(
CL1 + CS1 + CV _ Low
)
(
CL2 + CS 2 + CV _ Low
)
• CLow is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
CLow determines the high frequency component on the TPR.
• CHigh is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
CHigh determines the low frequency component on the TPR.
⎛
⎜
⎞
⎟
1
1
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎠
Total Pull Range (TPR) =
−
⋅106
CLow
CHigh
⎛
⎝
⎞
⎟
⎠
⎛
⎝
⎞
⎟
C
0 C
1
C
0
C
0 C
1
C
0
2⋅
⋅ 1+
⎜
2⋅
⋅ 1+
⎜
⎠
Absolute Pull Range ꢁAPRꢂ = Total Pull Range – ꢁFrequency Tolerance + Frequency Stability + Agingꢂ
EXAMPLE CALCULATIONS
the inaccuracy due to aging is 15ppm. Third, though many
boards will not require load tuning capacitors ꢁCL1, CL2ꢂ, it is
recommended for long-term consistent performance of the
system that two tuning capacitor pads be placed into every
design.Typical values for the load tuning capacitors will range
from 0 to 4pF.
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal
parameters. For the numerical example below there were some
assumptions made. First, the stray capacitance ꢁCS1, CS2ꢂ, which
is all the excess capacitance due to board parasitic, is 4pF.
Second, the expected lifetime of the project is 5 years; hence
(
0 + 4pf + 29.6pf
0 + 4pf + 29.6pf
)
⋅
+
(
0 + 4pf + 29.6pf
)
= 16.8pf
(
0 + 4pf +15.4pf
0 + 4pf +15.4pf
)
⋅
+
(
0 + 4pf +15.4pf
)
= 9.7 pf
CHigh
=
CLow
=
(
)
(
0 + 4pf + 29.6pf
)
(
)
(0 + 4pf +15.4pf
)
⎛
⎜
⎞
⎟
1
1
6
⎜
⎟
TPR =
−
⋅10 ⋅ = 226.5ppm
9.7 pF
16.8pF
⎛
⎞
⎟
⎛
⎞
⎟
⎜
⎜
⎟
⎟
2⋅220⋅ 1+
2⋅220⋅ 1+
⎜
⎜
4pF
4pF
⎝
⎠
⎝
⎠
⎝
⎠
TPR = 113.25ppm
APR = 113.25ppm – ꢁ20ppm + 20ppm + 15ppmꢂ = 58.25ppm
The example above will ensure a total pull range of with better pullability ꢁC0/C1 ratioꢂ can be used. Also, with the
113.25 ppm with an APR of 58.25ppm. Many times, board equations above, one can vary the frequency tolerance,
designers may select their own crystal based on their temperature stability, and aging or shunt capacitance to achieve
application. If the application requires a tighter APR, a crystal the required pullability.
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ICS81006
Integrated
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VCXO-TO-6 LVCMOS OUTPUTS
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CONTROL PINS:
LVCMOS OUTPUT:
All control pins have internal pull-ups or pull-downs; additional All unused LVCMOS output can be left floating. We
resistance is not required but can be added for additional recommend that there is no trace attached.
protection. A 1kΩ resistor can be used.The VC pin can not be
floated.
SCHEMATIC EXAMPLE
Figure 2 shows an example of ICS81006 application sche- drivers, series termination example is shown in the sche-
matic.The decoupling capacitors should be located as close matic. Additional termination approaches are shown in the
as possible to the power pin. For the LVCMOS 20Ω output LVCMOS Termination Application Note.
Pull-up VDD
example
VDDO
R4
1K
Quartz crystal should be
placed as close to the
device as possible.
VDD
R1
30
Zo = 50
C1
U1
SPARE
1
2
3
4
5
15
14
13
12
11
XTAL_IN
XTAL_OUT
VDD
GND
Q2
VDDO
Q3
XTAL
VC
DIV_SEL_Q5
GND
C2
SPARE
VC
VC = 0V to VDD
81006
Pull-down
example
R3
1K
R2
30
Zo = 50
VDD
R5
1K
ꢁU1-3ꢂ
ꢁU1-ꢀꢂ
ꢁU1-13ꢂ ꢁU1-17ꢂ
VDD
VDDO
Unused outputs can be left floating. There should be
no trace attached to unused outputs. Device
characterized and specification limits set with all
outputs terminated.
C7
10uf
C6
0.1uF
C5
0.1uF
C4
0.1uF
C3
0.1uF
FIGURE 2. ICS81006 SCHEMATIC EXAMPLE
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ICS81006
Integrated
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VCXO-TO-6 LVCMOS OUTPUTS
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOWT ABLE FOR 20 LEAD VFQFN
θ
JA by Velocity (Meters Per Second)
0
1
2.5
116.ꢀ°C/W
33.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
141.7°C/W
38.5°C/W
126.0°C/W
35.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS81006 is: ꢀ83
81006AK
www.icst.com/products/hiperclocks.html
REV.A JANUARY 4, 2006
12
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
PACKAGE OUTLINE - K SUFFIX FOR 20 LEAD VFQFN
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
20
0.80
0
1.0
A1
A3
b
0.05
0.25 Reference
0.18
0.30
e
0.50 BASIC
ND
NE
D
5
5
4.0
D2
E
0.75
2.80
4.0
E2
L
0.75
0.35
2.80
0.75
Reference Document: JEDEC Publication ꢀ5, MO-220
81006AK
www.icst.com/products/hiperclocks.html
REV.A JANUARY 4, 2006
13
ICS81006
Integrated
Circuit
Systems, Inc.
VCXO-TO-6 LVCMOS OUTPUTS
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS81006AK
Marking
Package
Shipping Packaging
tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
81006A
81006A
TBD
20 lead VFQFN
ICS81006AKT
20 lead VFQFN
2500 tape & reel
tube
ICS81006AKLF
ICS81006AKLFT
20 lead "Lead-Free" VFQFN
20 lead "Lead-Free" VFQFN
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated ꢁICSꢂ assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
81006AK
www.icst.com/products/hiperclocks.html
REV.A JANUARY 4, 2006
14
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