ICS813001AGIT [ICSI]
DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL; 双VCXO W / 3.3V ， 2.5V LVPECL FEMTOCLOCK -TM PLL
| 型号： | ICS813001AGIT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DUAL VCXO W/3.3V, 2.5V LVPECL FEMTOCLOCK-TM PLL |
| 文件： | 总18页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
ICS
FEATURES
The ICS813001I is a dual VCXO + FemtoClock™ • One 3.3V or 2.5V LVPECL output pair
Multiplier designed for use in Discrete PLL
• Two selectable crystal oscillator interfaces for the VCXO,
one differential clock or one LVCMOS/LVTTL clock inputs
HiPerClockS™
loops. Two selectable external VCXO crystals
allow the device to be used in multi-rate appli-
cations, where a given line card can be
• CLK1/nCLK1 supports the following input types:
LVPECL, LVDS, LVHSTL, SSTL, HCSL
switched, for example, between 1Gb Ethernet (125MHz
system reference clock) and 1Gb Fibre Channel
(106.25MHz system reference clock) modes. Of course,
a multitude of other applications are also possible such
as switching between 74.25MHz and 74.175824MHz
for HDTV, switching between SONET, FEC and non FEC
rates, etc.
• Crystal operating frequency range: 14MHz - 24MHz
• VCO range: 490MHz - 640MHz
• Output frequency range: 40.83MHz - 640MHz
• VCXO pull range: 100ppm (typical)
• Supports the following applications (among others):
SONET, Ethernet, Fibre Channel, HDTV, MPEG
The ICS813001I is a two stage device – a VCXO followed
by a FemtoClock PLL. The FemtoClock PLL can multiply
the crystal frequency of the VCXO to provide an output
frequency range of 40.83MHz to 640MHz, with a random
rms phase jitter of less than 1ps (12kHz – 20MHz). This
phase jitter performance meets the requirements of 1Gb/
10Gb Ethernet, 1Gb, 2Gb, 4Gb and 10Gb Fibre Channel,
and SONET up to OC48. The FemtoClock PLL can also be
bypassed if frequency multiplication is not required. For
testing/debug purposes, de-assertion of the output enable
pin will place both Q and nQ in a high impedance state.
• RMS phase jitter @ 622.08MHz (12kHz - 20MHz):
0.84 (typical)
• Supply voltage modes:
VCC/VCCO
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free
compliant packages
BLOCK DIAGRAM
Pullup
VCO_SEL
Pulldown
CLK_SEL0
Pullup
CLK_SEL1
Pulldown
CLK0
0 0
Pulldown
0
Output Divider N
CLK1
Pullup
0 1
N2:N0
nCLK1
000 ÷1
001 ÷2
010 ÷3
VCO
490-640MHz
1
PD
XTAL_IN0
Q
nQ
1 0
011 ÷4 (default)
100 ÷5
(default)
XTAL_OUT0
XTAL_IN1
Feedback Divider M
101 ÷6
110 ÷8
111 ÷12
VCXO
PIN ASSIGNMENT
M2:M0
VCO_SEL
1
CLK_SEL1
CLK_SEL0
OE
24
23
22
21
20
19
18
17
000 ÷16
001 ÷20
010 ÷22
011 ÷24
100 ÷25 (default)
101 ÷32
110 ÷40
111 MR
N0
2
1 1
N1
N2
3
XTAL_OUT1
4
M2
5
6
VCCO
Q
M1
M0
nQ
7
CLK1
VC
M2
M1
VEE
VCCA
VCC
8
nCLK1
CLK0
Pullup
9
16
15
14
13
Pulldown
Pulldown
Pulldown
Pullup
10
11
12
VC
XTAL_OUT1
XTAL_IN0
XTAL_OUT0
M0
N2
XTAL_IN1
ICS813001I
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
package body
N1
Pullup
N0
Pullup
OE
G Package
Top View
813001AGI
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REV.A SEPTEMBER 2, 2005
1
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Νυμ βερ
Ναμ ε
VCO_SEL
N0, N1
N2
Τψπε
Δεσχριπτιον
1
2, 3
4
Input
Input
Pullup
Pullup
VCO select pin. LVCMOS/LVTTL interface levels.
Output divider select pins. Default value = ÷4.
LVCMOS/LVTTL interface levels.
Pulldown
Input
5
VCCO
Power
Ouput
Power
Power
Power
Output supply pin.
6, 7
8
Q, nQ
VEE
Differential output pair. LVPECL interface levels.
Negative supply pin.
9
VCCA
Analog supply pin.
10
VCC
Core supply pin.
11
12
13
14
XTAL_OUT1,
XTAL_IN1
XTAL_OUT0,
XTAL_IN0
Parallel resonant crystal interface. XTAL_OUT1 is the output,
XTAL_IN1 is the input.
Parallel resonant crystal interface. XTAL_OUT0 is the output,
XTAL_IN0 is the input.
Input
Input
15
16
VC
Input
Input
Input
Input
Input
Input
VCXO control voltage input.
CLK0
nCLK1
CLK1
M0, M1
M2
Pulldown LVCMOS/LVTTL clock input.
Pullup Inverting differential clock input.
Pulldown Non-inverting differential clock input.
17
18
19, 20
21
Pulldown
Pullup
Feedback divider select pins. Default value = ÷25.
LVCMOS/LVTTL interface levels.
Output enable. When HIGH, the output is active. When LOW, the output
is in a high impedance state. LVCMOS/LVTTL interface levels.
22
OE
Input
Pullup
23
24
CLK_SEL0
CLK_SEL1
Input
Input
Pulldown
Pullup
Clock select pin. LVCMOS/LVTTL interface levels. Refer to Table 3.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
RPULLUP Input Pullup Resistor
51
51
TABLE 3. CONTROL INPUT FUNCTIONTABLE
Inputs
CLK_SEL1
CLK_SEL0
Selected Input
CLK0
0
0
1
1
0
1
0
1
CLK1, nCLK1
XTAL0
XTAL1
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REV.A SEPTEMBER 2, 2005
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ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO (LVPECL)
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
70°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC =VCCA =VCCO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
130
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
10
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VCC =VCCA = 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.135
3.135
2.375
3.3
3.3
2.5
3.465
3.465
2.625
130
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
10
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA =VCCO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
2.375
2.375
2.375
2.5
2.5
2.5
2.625
2.625
2.625
125
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
10
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ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
TABLE 4C. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
CC = 3.3V
Minimum Typical Maximum Units
V
2.0
1.7
-0.3
-0.3
0
VCC + 0.3
VCC + 0.3
0.8
V
V
V
V
V
VIH
Input High Voltage
VCC = 2.5V
VCC = 3.3V
VCC = 2.5V
VIL
Input Low Voltage
0.7
VC
VCXO Control Voltage
VCC
V
CC = VIN = 3.465V
or 2.625V
N2, M0, M1,
CLK0, CLK_SEL0
150
5
µA
µA
Input
High Current
IIH
VCC = VIN = 3.465V
N0, N1, M2,
VCO_SEL, CLK_SEL1
or 2.625V
VCC = 3.465V or 2.625V,
VIN = 0V
N2, M0, M1,
CLK0, CLK_SEL0
-5
µA
Input
Low Current
IIL
VCC = 3.465V or 2.625V,
N0, N1, M2,
VCO_SEL, CLK_SEL1
-150
-100
µA
µA
VIN = 0V
IVC
Input Current cƒVc pin
VCC = 3.465V or 2.625V
100
TABLE 4D. DIFFERENTIAL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
V
IN = VCC = 3.465V
or 2.625V
CLK1
150
5
µA
µA
µA
µA
IIH
Input High Current
VIN = VCC = 3.465V
or 2.625V
VIN = 0V, VCC = 3.465V
or 2.625V
nCLK1
CLK1
-5
IIL
Input Low Current
V
IN = 0V, VCC = 3.465V
nCLK1
-150
or 2.625V
VPP
Peak-to-Peak Input Voltage
0.15
1.3
V
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
VEE + 0.5
VCC - 0.85
NOTE 1: Common mode voltage is defined as VIH.
NOTE 2: For single ended appliations, the maximum input voltage for CLK1, nCLK1 is VCC + 0.3V.
TABLE 4E. LVPECL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
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REV.A SEPTEMBER 2, 2005
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ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
TABLE 5A. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
VCO_SEL = 1
40.83
640
MHz
RMS Phase Jitter, (Random);
NOTE 1
tjit(Ø)
622.08MHz (12kHz - 20MHz)
0.84
ps
fVCO
PLL VCO Lock Range
Output Rise/Fall Time
490
250
43
640
500
57
MHz
ps
tR / tF
20ꢀ to 80ꢀ
N ÷ 1
ꢀ
odc
Output Duty Cycle
N ≠ ÷1
48
52
ꢀ
NOTE 1: Phase jitter using a crystal interface.
TABLE 5B. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, VCCO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
VCO_SEL = 1
40.83
640
MHz
RMS Phase Jitter, (Random);
NOTE 1
tjit(Ø)
622.08MHz (12kHz - 20MHz)
0.87
ps
fVCO
PLL VCO Lock Range
Output Rise/Fall Time
490
250
43
640
500
57
MHz
ps
tR / tF
20ꢀ to 80ꢀ
N ÷ 1
ꢀ
odc
Output Duty Cycle
N ≠ ÷1
48
52
ꢀ
NOTE 1: Phase jitter using a crystal interface.
TABLE 5C. AC CHARACTERISTICS, VCC = VCCA = VCCO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
VCO_SEL = 1
40.83
640
MHz
RMS Phase Jitter, (Random);
NOTE 1
tjit(Ø)
622.08MHz (12kHz - 20MHz)
1.2
ps
fVCO
PLL VCO Lock Range
Output Rise/Fall Time
490
250
43
640
500
57
MHz
ps
tR / tF
20ꢀ to 80ꢀ
N ÷ 1
ꢀ
odc
Output Duty Cycle
N ≠ ÷1
48
52
ꢀ
NOTE 1: Phase jitter using a crystal interface.
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ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
TYPICAL PHASE NOISE AT 622.08MHZ @ 3.3V
0
-10
-20
-30
-40
OC-12 Filter
622.08MHz
RMS Phase Jitter (Random)
12kHz to 20MHz = 0.84ps (typical)
-50
-60
-70
Raw Phase Noise Data
-80
-90
-100
-110
-120
-130
-140
Phase Noise Result by adding
Sonet OC-12 Filter to raw data
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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REV.A SEPTEMBER 2, 2005
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ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
2.8V 0.04V
2V
SCOPE
SCOPE
VCC,
VCCA,
VCCO
VCC,
VCCA
Qx
Qx
VCCO
LVPECL
LVPECL
VEE
nQx
nQx
VEE
-0.5V 0.125V
-1.3V 0.165V
3.3V CORE/3.3V LVPECL OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
2V
VCC
SCOPE
VCC,
VCCA,
VCCO
Qx
nCLK1
VPP
VCMR
Cross Points
LVPECL
CLK1
VEE
nQx
VEE
-0.5V 0.125V
DIFFERENTIAL INPUT LEVELS
2.5V CORE/2.5V LVPECL OUTPUT LOAD AC TEST CIRCUIT
Q
Phase Noise Plot
nQ
tPW
tPERIOD
Phase Noise Mask
tPW
tPERIOD
odc =
x 100ꢀ
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
Clock
Outputs
20ꢀ
OUTPUT RISE/FALL TIME
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REV.A SEPTEMBER 2, 2005
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ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERINGT ECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS813001I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V or 2.5V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
capacitor should be connected to each VCCA
.
FIGURE 1. POWER SUPPLY FILTERING
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position the V_REF
single ended levels. The reference voltage V_REF = VCC/2 is in the center of the input voltage swing. For example, if the
generated by the bias resistors R1, R2 and C1.This bias circuit input clock swing is only 2.5V and VCC = 3.3V, V_REF should be
should be located as close as possible to the input pin.The ratio 1.25V and R2/R1 = 0.609.
VCC
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV.A SEPTEMBER 2, 2005
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ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
VCXO CRYSTAL SELECTION
Choosing a crystal with the correct characteristics is one of range and accuracy of a VCXO. Below are the key variables
the most critical steps in using a Voltage Controlled Crystal and an example of using the crystal parameters to calculate
Oscillator (VCXO). The crystal parameters affect the tuning the tuning range of the VCXO.
VC
- Control voltage used to tune
frequency
VC
ControlVoltage
Oscillator
➤
CV
- Varactor capacitance, varies due to
change in control voltage
the
C
C
V
V
CL1, CL2 - Load tuning capacitance used for fine
tuning or centering nominal
frequency
VCXO (Internal)
CS1, CS2
- Stray Capacitance caused by pads,
vias, and other board parasitics
XTAL
CS1
CS2
CL1
CL2
Optional
FIGURE 3. VCXO OSCILLATOR CIRCUIT
TABLE 6.EXAMPLE CRYSTAL PARAMETERS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fN
fT
fS
Nominal Frequency
Frequency Tolerance
Frequency Stability
Operating Temperature Range
Load Capacitance
Shunt Capacitance
Pullability Ratio
14
24
20
20
70
MHz
ppm
ppm
°C
0
CL
12
4
pF
CO
pF
C1, C2
ESR
220
240
20
1
Equivalent Series Resistance
Drive Level
mW
ppm
Aging @ 25°C
3 per year
Mode of Operation
Fundamental
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REV.A SEPTEMBER 2, 2005
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ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
TABLE 7.VARACTOR PARAMETERS
Symbol Parameter
Test Conditions
VC = 0V
Minimum Typical Maximum Units
CV_LOW
CV_HIGH
Low Varactor Capacitance
High Varactor Capacitance
15
pF
pF
VC = 3.3V
27.4
FORMULAS
CL1 + CS1 + CV _ High
⋅
+
CL2 + CS 2 + CV _ High
CL1 + CS1 + CV _ Low
⋅
+
CL2 + CS 2 + CV _ Low
CHigh
=
CLow
=
(
CL1 + CS1 + CV _ High
)
(
CL2 + CS 2 + CV _ High
)
(
CL1 + CS1 + CV _ Low
)
(
CL2 + CS 2 + CV _ Low
)
• CLow is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.
CLow determines the high frequency component on the TPR.
• CHigh is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.
CHigh determines the low frequency component on the TPR.
⎛
⎜
⎞
⎟
1
1
⎜
⎜
⎜
⎝
⎟
⎟
⎟
⎠
Total Pull Range (TPR) =
−
⋅106
CLow
CHigh
⎛
⎝
⎞
⎟
⎠
⎛
⎝
⎞
⎟
C
0 C
1
C
0
C
0 C
1
C
0
2⋅
⋅ 1+
⎜
2⋅
⋅ 1+
⎜
⎠
Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)
EXAMPLE CALCULATIONS
is 5 years; hence the inaccuracy due to aging is 15ppm.
Third, though many boards will not require load tuning
capacitors (CL1, CL2), it is recommended for long-term
consistent performance of the system that two tuning
capacitor pads be placed into every design. Typical values
for the load tuning capacitors will range from 0 to 4pF.
Using the tables and figures above, we can now calculate the
TPR and APR of the VCXO using the example crystal
parameters. For the numerical example below there were
some assumptions made. First, the stray capacitance (CS1,
CS2), which is all the excess capacitance due to board
parasitic, is 4pF. Second, the expected lifetime of the project
(0 + 4pƒ + 15pƒ ) · (0 + 4pƒ + 15pƒ )
(0 + 4pƒ + 27.4pƒ ) · (0 + 4pƒ + 27.4pƒ )
CLow
=
CHigh =
= 9.5pƒ
= 15.7pƒ
(0 + 4pƒ + 15pƒ ) · (0 + 4pƒ + 15pƒ )
(0 + 4pƒ + 27.4pƒ ) · (0 + 4pƒ + 27.4pƒ )
⎞
⎟
1
1
= · 106 · = 212ppm
–
TPR=
⎟
⋅1
⎞
9.5pƒ
15.7pƒ
⎟
⎟
2· 220 ·
(
1 +
)
2· 220 ·
(
1 +
)
⎟
4pƒ
4pƒ
⎠
⎠
TPR = 106ppm
APR = 106ppm – (20ppm + 20ppm + 15ppm) = 51ppm
The example above will ensure a total pull range of with better pullability (C0/C1 ratio) can be used. Also, with the
equations above, one can vary the frequency tolerance,
106 ppm with an APR of 51ppm. Many times, board
designers may select their own crystal based on their temperature stability, and aging or shunt capacitance to
application. If the application requires a tighter APR, a crystal achieve the required pullability.
813001AGI
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REV.A SEPTEMBER 2, 2005
10
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 4A to4E show inter- For example in Figure 4A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 4A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 4B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 4C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 4D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 4E. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
813001AGI
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REV.A SEPTEMBER 2, 2005
11
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVPECL OUTPUT
For applications not requiring the use of the crystal oscillator All unused LVPECL outputs can be left floating. We
input, both XTAL_IN and XTAL_OUT can be left floating. recommend that there is no trace attached. Both sides of the
Though not required, but for additional protection, a 1kΩ differential output pair should either be left floating or
resistor can be tied from XTAL_IN to ground.
terminated.
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
VC input pin - do not float, must be biased.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical ter-
mination for LVPECL outputs. The two different layouts
mentioned are recommended only as guidelines.
Matched impedance techniques should be used to maxi-
mize operating frequency and minimize signal distor-
tion. Figures 5A and 5B show two different layouts which
are recommended only as guidelines. Other suitable
clock layouts may exist and it would be recommended
that the board designers simulate to guarantee compat-
ibility across all printed circuit and clock component pro-
cess variations.
FOUT and nFOUT are low impedance follower outputs
that generate ECL/LVPECL compatible outputs. There-
fore, terminating resistors (DC current path to ground)
or current sources must be used for functionality. These
outputs are designed to drive 50Ω transmission lines.
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 5B. LVPECL OUTPUTT ERMINATION
www.icst.com/products/hiperclocks.html
FIGURE 5A. LVPECL OUTPUTTERMINATION
813001AGI
REV.A SEPTEMBER 2, 2005
12
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
TERMINATION FOR 2.5V LVPECL OUTPUT
Figure 6A and Figure 6B show examples of termination for close to ground level. The R3 in Figure 6B can be eliminated
2.5V LVPECL driver.These terminations are equivalent to ter- and the termination is shown in Figure 6C.
minating 50Ω to VCC - 2V. For VCCO = 2.5V, the VCCO - 2V is very
2.5V
2.5V
2.5V
VCCO=2.5V
VCCO=2.5V
R1
R3
250
250
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
Zo = 50 Ohm
+
-
+
-
2,5V LVPECL
Driver
2,5V LVPECL
Driv er
R1
50
R2
50
R2
62.5
R4
62.5
R3
18
FIGURE 6A. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
FIGURE 6B. 2.5V LVPECL DRIVERTERMINATION EXAMPLE
2.5V
VCCO=2.5V
Zo = 50 Ohm
+
Zo = 50 Ohm
-
2,5V LVPECL
Driver
R1
50
R2
50
FIGURE 6C. 2.5V LVPECLTERMINATION EXAMPLE
813001AGI
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REV.A SEPTEMBER 2, 2005
13
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS813001I.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS813001I is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 130mA = 450.45mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with output switching) = 450.45mW + 30mW = 480.5mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 70°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.481W * 65°C/W = 116.3°C. This is below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8.THERMAL RESISTANCE θJA FOR 24-PIN TSSOP, FORCED CONVECTION
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
813001AGI
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REV.A SEPTEMBER 2, 2005
14
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT ANDT ERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 0.9V
CCO_MAX
OH_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V ) =
OH_MAX
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
_MAX
CCO
OH_MAX
CCO_MAX
L
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
_MAX
CCO
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
813001AGI
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REV.A SEPTEMBER 2, 2005
15
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOWT ABLE FOR 24 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS813001I is: 3948
813001AGI
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REV.A SEPTEMBER 2, 2005
16
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 10. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
813001AGI
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REV.A SEPTEMBER 2, 2005
17
ICS813001I
DUAL VCXO W/3.3V, 2.5V LVPECL
FEMTOCLOCK™ PLL
Integrated
Circuit
Systems, Inc.
TABLE 11. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS813001AGI
ICS813001AGIT
ICS813001AGILF
ICS813001AGILFT
ICS813001AGI
ICS813001AGI
ICS813001AGIL
ICS813001AGIL
24 Lead TSSOP
24 Lead TSSOP
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an LF suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
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REV.A SEPTEMBER 2, 2005
18
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