ICS83023AMIT [ICSI]
DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER; 差分至LVCMOS翻译/缓冲器
| 型号： | ICS83023AMIT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DIFFERENTIAL-TO-LVCMOS TRANSLATOR/BUFFER |
| 文件： | 总12页 (文件大小：156K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOSTRANSLATOR /BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
Features
The ICS83023I is a dual, 1-to-1 Differential-to-
• Two LVCMOS / LVTTL outputs
ICS
LVCMOS Translator/Fanout Buffer and a mem-
ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The differen-
tial inputs can accept most differential signal
• Two differential CLKx, nCLKx input pairs
HiPerClockS™
• CLK, nCLK pairs can accept the following differential
input levels: LVDS, LVPECL, LVHSTL, SSTL, HCSL
types (LVDS, LVHSTL, LVPECL, SSTL, and HCSL) and
translate into two single-ended LVCMOS outputs. The small
8-lead SOIC footprint makes this device ideal for use in ap-
plications with limited board space.
• Maximum output frequency: 350MHz (typical)
• Output skew: 60ps (maximum)
• Part-to-part skew: 500ps (maximum)
• Additive phase jitter, RMS: 0.14ps (typical)
• Small 8 lead SOIC package saves board space
• 3.3V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK0
nCLK0
Q0
CLK0
nCLK0
nCLK1
CLK1
VDD
Q0
1
2
3
4
8
7
6
5
Q1
GND
CLK1
nCLK1
Q1
ICS83023I
8-Lead SOIC
3.8mm x 4.8mm x 1.47mm package body
M Package
Top View
83023AMI
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1
ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOSTRANSLATOR /BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
CLK0
nCLK0
nCLK1
CLK1
GND
Q1
Type
Description
1
2
3
4
5
6
7
8
Input
Input
Pulldown Non-inverting differential clock input.
Pullup
Pullup
Inverting differential clock input.
Inverting differential clock input.
Input
Input
Pulldown Non-inverting differential clock input.
Power supply ground.
Power
Output
Output
Power
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Positive supply pin.
Q0
VDD
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
V
DD = 3.6V
23
pF
RPULLUP
Input Pullup Resistor
51
51
7
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT
Output Impedance
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ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOSTRANSLATOR /BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Func-
tional operation of product at these conditions or any condi-
tions beyond those listed in the DC Characteristics or AC
Characteristics is not implied. Exposure to absolute maxi-
mum rating conditions for extended periods may affect prod-
uct reliability.
Supply Voltage, V
4.6V
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
I
Outputs, VO
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol
VDD
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Positive Supply Voltage
Positive Supply Current
3.0
3.3
3.6
20
V
IDD
mA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.6
V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Section, 3.3V Output Load Test Circuit.
TABLE 3C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VDD = 3.6V
VIN = VDD = 3.6V
IN = 0V, VDD = 3.6V
IN = 0V, VDD = 3.6V
Minimum Typical Maximum Units
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
5
µA
µA
µA
µA
V
150
V
V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
V
DD - 0.85
V
NOTE 1: For single-ended applications, the maximum input voltage for CLKx, nCLKx is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOSTRANSLATOR /BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4. AC CHARACTERISTICS, VDD = 3.3V 0.3V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
fMAX
Maximum Output Frequency
350
2.1
MHz
ns
tPD
Propagation Delay; NOTE 1
Output Skew; NOTE 2, 4
1.8
2.4
60
tsk(o)
tsk(pp)
ps
Part-to-Part Skew; NOTE 3, 4
500
ps
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter Section
100MHz, Integration Range
(637kHz-10MHz)
tjit
0.14
ps
tR
tF
Output Rise Time
Output Fall Time
0.8V to 2V
0.8V to 2V
f ≤ 166MHz
f > 166MHz
100
100
45
250
250
50
400
400
55
ps
ps
%
%
odc
Output Duty Cycle
43
50
57
All parameters measured at fMAX unless noted otherwise. See Parameter Measurement Information.
NOTE 1: Measured from the differential input crossing point to VDD/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDD/2. Input clocks are phase aligned.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDD/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
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ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOSTRANSLATOR /BUFFER
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
ratio of the power in the 1Hz band to the power in the funda-
mental. When the required offset is specified, the phase noise
is called a dBc value, which simply means dBm at a specified
offset from the fundamental. By investigating jitter in the fre-
quency domain, we get a better understanding of its effects
on the desired application over the entire time record of the
signal. It is mathematically possible to calculate an expected
bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the
fundamental compared to the power of the fundamental is
called the dBc Phase Noise. This value is normally expressed
using a Phase noise plot and is most often the specified plot
in many applications. Phase noise is defined as the ratio of
the noise power present in a 1Hz band at a specified offset
from the fundamental frequency to the power value of the
fundamental. This ratio is expressed in decibels (dBm) or a
0
-10
-20
-30
-40
-50
Additive Phase Jitter @ 100MHz
(12kHz to 20MHz)
= 0.14ps typical
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measure- above. The device meets the noise floor of what is shown, but
ments have issues. The primary issue relates to the limita- can actually be lower. The phase noise is dependant on the
tions of the equipment. Often the noise floor of the equipment input source and measurement equipment.
is higher than the noise floor of the device. This is illustrated
83023AMI
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ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOSTRANSLATOR /BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V 0.15V
VDD
SCOPE
VDD
nCLK
CLK
Qx
LVCMOS
VPP
VCMR
Cross Points
GND
GND
-1.65V 0.15V
3.3V OUTPUT LOAD ACTEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
VDD
PART 1
Qx
VDD
2
Qx
Qy
2
VDD
2
VDD
PART 2
Qy
2
tsk(o)
tsk(pp)
PART-TO-PART SKEW
OUTPUT SKEW
nCLK0, nCLK1
CLK0, CLK1
VDD
2
Q0, Q1
tPW
tPERIOD
VDD
2
t
Q0, Q1
tPW
tPERIOD
PD
x 100%
odc =
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
2V
2V
0.8V
0.8V
Clock
Outputs
tR
tF
OUTPUT RISE/FALLTIME
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REV.B JANUARY 18, 2006
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ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOSTRANSLATOR /BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin. The
ratio of R1 and R2 might need to be adjusted to position the
V_REF in the center of the input voltage swing. For example, if
the input clock swing is only 2.5V andVDD = 3.3V, V_REF should
be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK/nCLK INPUT:
LVCMOS OUTPUT:
For applications not requiring the use of the differential input, All unused LVCMOS output can be left floating. We
both CLK and nCLK can be left floating. Though not required, recommend that there is no trace attached.
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
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REV.B JANUARY 18, 2006
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ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOSTRANSLATOR /BUFFER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, faces suggested here are examples only. Please consult with
HCSL and other differential signals. Both VSWING and VOH must the vendor of the driver component to confirm the driver termi-
meet the VPP and VCMR input requirements. Figures 2A to 2E nation requirements. For example in Figure 2A, the input ter-
show interface examples for the HiPerClockS CLK/nCLK in- mination applies for ICS HiPerClockS LVHSTL drivers. If you
put driven by the most common driver types. The input inter- are using an LVHSTL driver from another vendor, use their
termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 2A. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 2B. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
125
R4
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiv er
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS CLK/nCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 2E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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REV.B JANUARY 18, 2006
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ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOSTRANSLATOR /BUFFER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 5. θJAVS. AIR FLOWTABLE FOR 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83023I is: 416
Pin-to-pin compatible with MC100EPT23
83023AMI
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REV.B JANUARY 18, 2006
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ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOSTRANSLATOR /BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS
Millimeters
MINIMUN MAXIMUM
SYMBOL
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
83023AMI
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REV.B JANUARY 18, 2006
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ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOSTRANSLATOR /BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS83023AMI
Marking
83021AMI
83021AMI
83023AIL
83023AIL
Package
8 lead SOIC
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS83023AMIT
ICS83023AMILF
ICS83023AMILFT
8 lead SOIC
2500 tape & reel
tube
8 lead "Lead-Free" SOIC
8 lead "Lead-Free" SOIC
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industiral applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
83023AMI
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REV.B JANUARY 18, 2006
11
ICS83023I
DUAL, 1-TO-1
DIFFERENTIAL-TO-LVCMOSTRANSLATOR /BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
Ordering Information Table - corrected Part/Order Number for Tape & Reel to
read ICS83023AMIT from ICS83023AMI.
A
7
11
09/09/02
1
2
4
Features Section - added Additive Phase Jitter and Lead-Free bullets.
Pin Characteristics Table - changed CIN from 4pF max. to 4pF typical.
AC Characteristics Table - added Additive Phase Jitter row.
Added Additive Phase Jitter Plot.
T2
T4
5
B
B
12/12/05
1/18/08
7
8
11
Added Recommendations for Unused Input and Output Pins.
Added Differential Clock Input Interface.
Ordering Information Table - added Lead-Free Part Number and Note.
Update datasheet format.
T7
T7
11
Ordering information Table - added Lead-Free marking.
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REV.B JANUARY 18, 2006
12
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