ICS8302AM-01 [ICSI]
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT; 低偏移， 1到2 LVCMOS / LVTTL扇出缓冲器W /互补输出
| 型号： | ICS8302AM-01 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER W/ COMPLEMENTARY OUTPUT |
| 文件： | 总8页 (文件大小：75K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8302-01
LOW SKEW, 1-TO-2 LVCMOS / LVTTL
FANOUT BUFFER W/ COMPLEMENTARY OUTPUT
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8302-01 is a low skew, 1-to-2
• Complementary LVCMOS / LVTTLoutput
,&6
LVCMOS/LVTTL Fanout Buffer w/Complemen-
tary Output and a member of the HiPerClockS™
family of High Performance Clock Solutions
from ICS. The ICS8302-01 has a single ended
• LVCMOS / LVTTL clock input accepts LVCMOS
or LVTTL input levels
HiPerClockS™
• Maximum output frequency: 250MHz
clock input. The single ended clock input accepts LVCMOS
or LVTTL input levels. The ICS8302-01 is characterized
at full 3.3V for input VDD, and mixed 3.3V and 2.5V for
output operating supply modes (VDDO). Guaranteed
output and part-to-part skew characteristics make the
ICS8302-01 ideal for clock distribution applications
demanding well defined performance and repeatability.
• Output skew: 165ps (maximum)
• Part-to-part skew: 800ps (maximum)
• Small 8 lead SOIC package saves board space
• Full 3.3V or 3.3V core, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
VDDO
VDD
Q
1
2
3
4
8
7
6
5
GND
VDDO
nQ
CLK
GND
Q
CLK
nQ
ICS8302-01
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
Top View
8302AM-01
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 10, 2002
1
ICS8302-01
LOW SKEW, 1-TO-2 LVCMOS / LVTTL
FANOUT BUFFER W/ COMPLEMENTARY OUTPUT
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDO
VDD
Type
Description
1, 6
2
Power
Power
Input
Output supply pins.
Core supply pin.
3
CLK
GND
nQ
Pulldown LVCMOS / LVTTL clock input.
Power supply ground.
4,7
5
Power
Output
Output
Complementary clock output. LVCMOS / LVTTL interface levels.
Clock output. LVCMOS / LVTTL interface levels.
8
Q
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
KΩ
KΩ
Ω
VDD, VDDO = 3.465V
22
16
51
51
7
Power Dissipation Capacitance
(per output)
CPD
VDD = 3.465V, VDDO = 2.625V
RPULLUP
Input Pullup Resistor
RPULLDOWN Input Pulldown Resistor
ROUT
Output Impedance
8302AM-01
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REV. A DECEMBER 10, 2002
2
ICS8302-01
LOW SKEW, 1-TO-2 LVCMOS / LVTTL
FANOUT BUFFER W/ COMPLEMENTARY OUTPUT
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
I
Outputs, VO
Package Thermal Impedance, θJA 112.7°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.465
3.465
13
V
Output Power Supply Voltage
Power Supply Current
3.135
3.3
V
mA
mA
IDDO
Output Supply Current
4
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
1.3
V
V
Input Low Voltage
-0.3
Input High Current CLK
Input Low Current CLK
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
50Ω to VDDO/2
150
µA
µA
V
IIL
-5
2.6
2.9
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -100µA
V
50Ω to VDDO/2
0.5
0.2
V
IOL = 100µA
V
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
250
2.7
165
800
800
55
MHz
ns
ps
ps
ps
%
tpLH
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
1.8
2.18
50
tsk(o)
tsk(pp)
tR / tF
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
20% to 80%
IJ 133MHz
300
45
odc
Output Duty Cycle
133MHz < IJ 250MHz
40
60
%
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8302AM-01
www.icst.com/products/hiperclocks.html
REV. A DECEMBER 10, 2002
3
ICS8302-01
LOW SKEW, 1-TO-2 LVCMOS / LVTTL
FANOUT BUFFER W/ COMPLEMENTARY OUTPUT
Integrated
Circuit
Systems, Incꢀ
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Positive Supply Voltage
3.465
2.625
13
V
Output Supply Voltage
Power Supply Current
Output Supply Current
2.375
2.5
V
mA
mA
IDDO
4
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
1.3
V
V
Input Low Voltage
-0.3
Input High Current CLK
Input Low Current CLK
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
50Ω to VDDO/2
150
µA
µA
V
IIL
-5
1.8
2.2
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -100µA
V
50Ω to VDDO/2
0.5
0.2
V
I
OL = 100µA
V
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
250
2.9
250
900
650
55
MHz
ns
ps
ps
ps
%
tpLH
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
1.9
tsk(o)
tsk(pp)
tR / tF
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
20% to 80%
IJ 133MHz
250
45
odc
Output Duty Cycle
133MHz < IJ 250MHz
40
60
%
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8302AM-01
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REV. A DECEMBER 10, 2002
4
ICS8302-01
LOW SKEW, 1-TO-2 LVCMOS / LVTTL
FANOUT BUFFER W/ COMPLEMENTARY OUTPUT
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VDD,VDDO = 1.65V±5%
2.05V±5% 1.25V±5%
SCOPE
SCOPE
VDD
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND = -1.65V±5%
GND = -1.25V±5%
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDD
VDDO
CLK
2
Q
2
VDDO
2
nQ
VDDO
2
Q
nQ
VDDO
2
tsk(o)
t
PD
PROPAGATION DELAY
OUTPUT SKEW
PART 1
VDD
Q
2
80%
80%
PART 2
VDDO
2
20%
20%
Q
Clock Outputs
nQ
t
t
VDDO
2
F
R
tsk(pp)
PART-TO-PART SKEW
OUTPUT RISE/FALL TIME
nQ
VDDO
VDDO
2
2
Q
tPW
tPERIOD
tPW
tPERIOD
odc =
odc & tPERIOD
8302AM-01
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REV. A DECEMBER 10, 2002
5
ICS8302-01
LOW SKEW, 1-TO-2 LVCMOS / LVTTL
FANOUT BUFFER W/ COMPLEMENTARY OUTPUT
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 5. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
128.5°C/W
115.5°C/W
112.7°C/W
103.3°C/W
97.1°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8302-01 is: 322
8302AM-01
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REV. A DECEMBER 10, 2002
6
ICS8302-01
LOW SKEW, 1-TO-2 LVCMOS / LVTTL
FANOUT BUFFER W/ COMPLEMENTARY OUTPUT
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - SUFFIX M
TABLE 6. PACKAGE DIMENSIONS
Millimeters
MINIMUN MAXIMUM
SYMBOL
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
8302AM-01
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REV. A DECEMBER 10, 2002
7
ICS8302-01
LOW SKEW, 1-TO-2 LVCMOS / LVTTL
FANOUT BUFFER W/ COMPLEMENTARY OUTPUT
Integrated
Circuit
Systems, Incꢀ
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS8302AM-01
Marking
8302A01
8302A01
Package
8 lead SOIC
Count
96 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
ICS8302AM-01T
8 lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8302AM-01
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REV. A DECEMBER 10, 2002
8
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