ICS8302AMLF [ICSI]
LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER; 低偏移， 1到2 LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS8302AMLF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-2 LVCMOS / LVTTL FANOUT BUFFER |
| 文件： | 总9页 (文件大小：133K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8302
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
LVCMOS / LVTTL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8302 is a low skew, 1-to-2 LVCMOS • 2 LVCMOS / LVTTL outputs
Fanout Buffer and a member of the
ICS
• LVCMOS / LVTTL clock input accepts LVCMOS
or LVTTL input levels
HiPerClockS™
HiPerClockS™family of High Performance
Clock Solutions from ICS. The ICS8302 has a
single ended clock input. The single ended clock
• Maximum output frequency: 200MHz
• Output skew: 25ps (typical)
input accepts LVCMOS or LVTTL input levels. The ICS8302
features a pair of LVCMOS/LVTTL outputs. The ICS8302 is
characterized at full 3.3V for inputVDD, and mixed 3.3V and
2.5V for output operating supply modes (VDDO). Guaran-
teed output and part-to-part skew characteristics make
the ICS8302 ideal for clock distribution applications demand-
ing well defined performance and repeatibility.
• Part-to-part skew: 250ps (typical)
• Small 8 lead SOIC package saves board space
• Full 3.3V or 3.3V core, 2.5V supply modes
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
VDDO
VDD
Q0
1
2
3
4
8
7
6
5
GND
VDDO
Q1
CLK
CLK
GND
Q1
ICS8302
8-Lead SOIC
3.8mm x 4.8mm, x 1.47mm package body
M Package
TopView
8302AM
www.icst.com/products/hiperclocks.html
REV. C JUNE 15, 2004
1
ICS8302
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDO
VDD
Type
Description
1, 6
2
Power
Power
Input
Output supply pins.
Core supply pin.
3
CLK
GND
Q1
Pulldown LVCMOS / LVTTL clock input.
Power supply ground.
4,7
5
Power
Output
Output
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
8
Q0
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
KΩ
VDD, VDDO = 3.465V
22
16
51
7
Power Dissipation Capacitance
(per output)
CPD
VDD = 3.465V, VDDO = 2.625V
RPULLDOWN Input Pulldown Resistor
ROUT
Output Impedance
5
12
Ω
8302AM
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REV. C JUNE 15, 2004
2
ICS8302
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
LVCMOS / LVTTL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
13
V
Output Power Supply Voltage
Power Supply Current
V
mA
mA
IDDO
Output Supply Current
4
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
1.3
V
V
Input Low Voltage
-0.3
Input High Current CLK
Input Low Current CLK
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
50Ω to VDDO/2
150
µA
µA
V
IIL
-5
2.6
2.9
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -100µA
V
50Ω to VDDO/2
0.5
0.2
V
IOL = 100µA
V
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
tsk(o)
tsk(pp)
tR
Output Frequency
200
2.8
85
MHz
ns
ps
ps
ps
ps
ꢀ
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
IJ 200MHz
1.9
2.35
25
250
800
800
800
55
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
300
300
45
tF
Output Fall Time
IJ 133MHz
odc
Output Duty Cycle
133MHz < IJ 200MHz
40
60
ꢀ
Parameters measured at fMAX unless otherwise noted.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8302AM
www.icst.com/products/hiperclocks.html
REV. C JUNE 15, 2004
3
ICS8302
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
2.375
3.3
2.5
3.465
2.625
13
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
mA
mA
IDDO
4
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
1.3
V
V
Input Low Voltage
-0.3
Input High Current CLK
Input Low Current CLK
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
50Ω to VDDO/2
150
µA
µA
V
IIL
-5
1.8
2.2
VOH
VOL
Output High Voltage
Output Low Voltage
IOH = -100µA
V
50Ω to VDDO/2
0.5
0.2
V
I
OL = 100µA
V
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
tpLH
tsk(o)
tsk(pp)
tR
Output Frequency
200
3.3
85
MHz
ns
ps
ps
ps
ps
ꢀ
Propagation Delay, Low-to-High; NOTE 1
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
IJ 200MHz
2.3
250
800
650
650
55
20ꢀ to 80ꢀ
20ꢀ to 80ꢀ
250
250
45
tF
Output Fall Time
IJ 133MHz
odc
Output Duty Cycle
133MHz < IJ 200MHz
40
60
ꢀ
Parameters measured at fMAX unless otherwise noted.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8302AM
www.icst.com/products/hiperclocks.html
REV. C JUNE 15, 2004
4
ICS8302
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
LVCMOS / LVTTL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
2.05V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
VDD
VDD
,
VDDO
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
PART 1
Qx
VDD
2
VDDO
Qx
2
VDD
VDDO
PART 2
Qy
Qy
2
2
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
VDD
80ꢀ
tF
80ꢀ
2
CLK
20ꢀ
20ꢀ
Clock
VDDO
tR
Outputs
2
Q0, Q1
t
PD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
VDDOX
2
VDDOX
VDDOX
2
2
Q0, Q1
tPW
tPERIOD
tPW
odc =
tPERIOD
OUTPUT PULSE WIDTH/PERIOD
8302AM
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REV. C JUNE 15, 2004
5
ICS8302
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
LVCMOS / LVTTL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 5. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8302 is: 322
8302AM
www.icst.com/products/hiperclocks.html
REV. C JUNE 15, 2004
6
ICS8302
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
LVCMOS / LVTTL FANOUT
BUFFER
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS
Millimeters
SYMBOL
MINIMUN
MAXIMUM
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
8302AM
www.icst.com/products/hiperclocks.html
REV. C JUNE 15, 2004
7
ICS8302
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-2
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS8302AM
Marking
Package
8 lead SOIC
Count
96 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
8302AM
8302AM
ICS8302AMT
8 lead SOIC on Tape and Reel
8 lead "Lead Free" SOIC
ICS8302AMLF
ICS8302AMLFT
8302AMLF
8302AMLF
96 per tube
2500
8 lead "Lead Free" SOIC on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8302AM
www.icst.com/products/hiperclocks.html
REV. C JUNE 15, 2004
8
ICS8302
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-2
LVCMOS / LVTTL FANOUT
BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
2
Date
T1
Pin Description table, revised VDD description.
T2
2
Pin Characteristics table, deleted RPULLUP row.
T3A & T3C
T4A & T4B
3, 4
3, 4
Power Supply table, changed VDD parameter to correspond with description.
B
2/4/03
AC Characteristics tables - added note "Parameters measured at fMAX unless
otherwise noted."
tpLH Test Conditions, added f ≤ 200MHz.
T2
T7
2
8
Pin Chararcteristics table - changed CIN 4pF max. to 4pF typical.
Added 5Ω min. and 12Ω max. to ROUT row.
Ordering Information table - added "Lead-Free" part number.
C
6/15/04
8302AM
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REV. C JUNE 15, 2004
9
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