ICS8304 [ICSI]
LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER; 低偏移， 1到4 LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS8304 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-4 LVCMOS / LVTTL FANOUT BUFFER |
| 文件： | 总9页 (文件大小：152K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8304
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4
LVCMOS / LVTTL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS8304 is a low skew, 1-to-4 Fanout • 4 LVCMOS / LVTTL outputs
Buffer and a member of the HiPerClockS ™
• LVCMOS / LVTTL clock input
ICS
HiPerClockS™
family of High Performance Clock Solutions
from ICS. The ICS8304 is characterized at
full 3.3V for inputVDD, and mixed 3.3V and 2.5V
for output operating supply modes (VDDO). Guaranteed out-
put and part-to-part skew characteristics make the
ICS8304 ideal for those clock distribution applications
demanding well defined performance and repeatability.
• Maximum output frequency: 200MHz
• Output skew: 45ps (maximum at 3.3V supply)
• Part-to-part skew: 500ps (maximum)
• Small 8 lead SOIC package saves board space
• 3.3V input, outputs may be either 3.3V or 2.5V supply modes
• Lead-Free package available
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
VDDO
VDD
Q3
Q2
Q1
Q0
1
2
3
4
8
7
6
5
CLK
GND
Q1
CLK
ICS8304
Q2
8-Lead SOIC, 150mil
3.9mm x 4.9mm, x 1.63mm package body
M Package
Q3
TopView
8304AM
www.icst.com/products/hiperclocks.html
REV. F SEPTEMBER 13, 2004
1
ICS8304
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDO
VDD
Type
Description
1
2
3
4
5
6
7
8
Power
Power
Input
Output supply pin.
Core supply pin.
CLK
GND
Q0
Pulldown LVCMOS / LVTTL clock input.
Power supply ground.
Power
Output
Output
Output
Output
Single clock output. LVCMOS / LVTTL interface levels.
Q1
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Single clock output. LVCMOS / LVTTL interface levels.
Q2
Q3
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
VDD, VDDO = 3.465V
15
12
pF
RPULLDOWN Input Pulldown Resistor
51
7
KΩ
ROUT
Output Impedance
5
Ω
8304AM
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REV. F SEPTEMBER 13, 2004
2
ICS8304
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4
LVCMOS / LVTTL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
112.7°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
15
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
mA
mA
IDDO
8
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
1.3
V
V
Input Low Voltage
Input High Current
Input Low Current
-0.3
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
Refer to NOTE 1
IOH = -16mA
150
µA
µA
V
IIL
-5
2.6
2.9
3
VOH
Output High Voltage
Output Low Voltage
V
IOH = -100uA
V
Refer to NOTE 1
IOL = 16mA
0.5
V
VOL
0.25
0.15
V
IOL = 100uA
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Section, "3.3V Output Load Test Circuit".
TABLE 3C. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.465
2.625
15
V
Output Supply Voltage
Power Supply Current
Output Supply Current
2.375
2.5
V
mA
mA
IDDO
8
8304AM
www.icst.com/products/hiperclocks.html
REV. F SEPTEMBER 13, 2004
3
ICS8304
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 3D. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VIH
VIL
IIH
Input High Voltage
2
VDD + 0.3
1.3
V
V
Input Low Voltage
-0.3
Input High Current
VDD = VIN = 3.465V
150
µA
µA
V
IIL
Input Low Current
VDD = 3.465V, VIN = 0V
-5
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Section,
"3.3V/2.5V Output Load Test Circuit".
TABLE 4A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Maximum Output Frequency
200
3.3
3.4
45
MHz
ns
ns
ps
ps
ps
ps
ꢀ
IJ 166MHz
166MHz < f ≤ 189.5MHz
ƒ= 133MHz
2.0
2.0
tpLH
Propagation Delay, Low-to-High; NOTE 1
tsk(o)
tsk(pp)
tR
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
500
500
500
60
30ꢀ to 70ꢀ
30ꢀ to 70ꢀ
f ≤ 189.5MHz
250
250
40
tF
Output Fall Time
odc
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 4B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Maximum Output Frequency
189.5
3.7
MHz
ns
ns
ps
ps
ps
ps
ꢀ
IJ 166MHz
166MHz < f ≤ 189.5MHz
ƒ= 133MHz
2.3
tpLH
Propagation Delay, Low-to-High; NOTE 1
2.15
3.55
60
tsk(o)
tsk(pp)
tR
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise Time
500
500
500
60
30ꢀ to 70ꢀ
30ꢀ to 70ꢀ
f ≤ 189.5MHz
250
250
40
tF
Output Fall Time
odc
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured
at VDDO/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
8304AM
www.icst.com/products/hiperclocks.html
REV. F SEPTEMBER 13, 2004
4
ICS8304
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4
LVCMOS / LVTTL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
2.05V 5ꢀ 1.25V 5ꢀ
SCOPE
SCOPE
VDD
VDD
,
VDDO
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
PART 1
VDD
VDD
Qx
2
Qx
2
PART 2
VDD
VDD
Qy
Qy
2
2
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
VDDO
70ꢀ
tF
70ꢀ
2
Q0:Q3
Pulse Width
tPERIOD
30ꢀ
30ꢀ
Clock
tR
Outputs
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
2
CLK
VDDO
2
Q0:Q3
t
PD
PROPAGATION DELAY
8304AM
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REV. F SEPTEMBER 13, 2004
5
ICS8304
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4
LVCMOS / LVTTL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 5. θJAVS. AIR FLOW TABLE FOR 8 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
128.5°C/W
103.3°C/W
500
115.5°C/W
97.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
153.3°C/W
112.7°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8304 is: 416
8304AM
www.icst.com/products/hiperclocks.html
REV. F SEPTEMBER 13, 2004
6
ICS8304
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4
LVCMOS / LVTTL FANOUT
BUFFER
PACKAGE OUTLINE - SUFFIX M FOR 8 LEAD SOIC
TABLE 6. PACKAGE DIMENSIONS - SUFFIX M
Millimeters
MINIMUN MAXIMUM
SYMBOL
N
A
A1
B
C
D
E
e
8
1.35
0.10
0.33
0.19
4.80
3.80
1.75
0.25
0.51
0.25
5.00
4.00
1.27 BASIC
H
h
5.80
0.25
0.40
0°
6.20
0.50
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-012
8304AM
www.icst.com/products/hiperclocks.html
REV. F SEPTEMBER 13, 2004
7
ICS8304
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 7. ORDERING INFORMATION
Part/Order Number
ICS8304AM
Marking
Package
Count
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
8304AM
8304AM
8 lead SOIC
96 per tube
2500
ICS8304AMT
8 lead SOIC on Tape and Reel
8 lead SOIC, "Lead Free/Annealed"
ICS8304AMLN
8304AMLN
96 per tube
8 lead SOIC, "Lead Free/Annealed"
on Tape and Reel
ICS8304AMLNT
ICS8304AMLF
ICS8304AMLFT
8304AMLN
8304AMLF
8304AMLF
2500
96 per tube
2500
0°C to 70°C
0°C to 70°C
0°C to 70°C
8 lead SOIC, "Lead Free"
8 lead SOIC, "Lead Free"
on Tape and Reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8304AM
www.icst.com/products/hiperclocks.html
REV. F SEPTEMBER 13, 2004
8
ICS8304
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-4
LVCMOS / LVTTL FANOUT
BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
B
T4A
3
• Revised tpLH (Propagation Delay) row from 2.3 Min. to 2 Min.
• Deleted tpHL row.
12/4/01
• Revised tsk(o) (Output Skew) row from 35 Max. to 80 Max.
• Revised tsk(pp) (Part-to-Part Skew) row from 200 Max. to 500 Max.
• General note changed from "...measured at 166MHz..." to
" ...measured at 150MHz..."
T4B
4
• Revised tpLH (Propagation Delay) row from 2.6 Min. to 2.3 Min.
• Deleted tpHL row.
• Revised tsk(o) (Output Skew) row from 35 Max. to 85 Max.
• Revised tsk(pp) (Part-to-Part Skew) row from 200 Max. to 500 Max.
• General note changed from "...measured at 166MHz..." to
" ...measured at 150MHz..."
C
T4A
T4B
3
4
• In AC table, revised tsk(o) row from 80ps Max. to 45ps Max.
Added f = 133MHz in Test Conditions column.
• In odc row, deleted test conditions.
• In notes, changed 150MHz to fMAX.
12/11/01
• In AC table, revised tsk(o) row from 80ps Max. to 60ps Max.
Added f = 133MHz in Test Conditions column.
• In odc row, deleted test conditions
• In notes, changed 150MHz to fMAX.
T7
10
3
In the Ordering Information table, Marking column, revised marking to read
8304AM from ICS8304AM.
LVCMOS/LVTTL DC Characteristics Table, added IOH and IOL Test Conditions
to VOH and VOL rows.
C
D
3/11/02
4/4/02
T3B
1
2
2
• Pin Assignment - adjusted dimensions.
T1
T2
• Pin Descriptions - changed VDD description to Core supply pin.
• Pin Characteristics - changed CIN max 4pF to typical 4pF.
Deleted R
row.
Added 5ΩPmULLinUP. and 12Ω max. to ROUT
.
E
4/13/04
T3A & T3C
T7
3 & 4
8
• Power Supply tables - changed VDD parameter from Power to Core.
• Ordering Information table - added "Lead Free/Annealed" marking.
Updated format throughout the data sheet.
Featues section, changed Maximum output frequency bullet from 166MHz to
200MHz.
1
4
T4A
T4B
T7
3.3V AC Table - changed 166MHz max. to 200MHz max.
Added another line for Propagation Delay.
F
F
6/1/04
Changed test conditions in Output Duty Cycle from 166MHz to 189.5MHz.
4
8
3.3V AC Table - changed 166MHz max. to 189.5MHz max.
Added another line for Propagation Delay.
Changed test conditions in Output Duty Cycle from 166MHz to 189.5MH
• Ordering Information table - added "Lead Free" marking.
9/13/04
8304AM
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REV. F SEPTEMBER 13, 2004
9
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