ICS8305AGIT [ICSI]
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER; 低偏移， 1到4 ，差分复用/ LVCMOS - TO- LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS8305AGIT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER |
| 文件： | 总15页 (文件大小：209K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS8305I is a low skew, 1-to-4, Differential/ • 4 LVCMOS/LVTTL outputs
ICS
LVCMOS-to-LVCMOS/LVTTL Fanout Buffer and a
• Selectable differential or LVCMOS/LVTTL clock inputs
HiPerClockS™
member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
ICS8305I has selectable clock inputs that accept
• CLK, nCLK pair can accept the following differential
input levels: LVPECL, LVDS, LVHSTL, HCSL, SSTL
either differential or single ended input levels.The clock enable is
internally synchronized to eliminate runt pulses on the outputs
during asynchronous assertion/deassertion of the clock enable
pin. Outputs are forced LOW when the clock is disabled. A sepa-
rate output enable pin controls whether the outputs are in the
active or high impedance state.
• LVCMOS_CLK supports the following input types:
LVCMOS, LVTTL
• Maximum output frequency: 350MHz
• Output skew: 40ps (maximum)
• Part-to-part skew: 700ps (maximum)
• Additive phase jitter, RMS: 0.04ps (typical)
• 3.3V core, 3.3V, 2.5V or 1.8V output operating supply
• -40°C to 85°C ambient operating temperature
• Lead-Free package fully RoHS compliant
Guaranteed output and part-to-part skew characteristics make
the ICS8305I ideal for those applications demanding well de-
fined performance and repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
GND
OE
VDD
16
15
14
13
12
11
10
9
Q0
VDDO
Q1
GND
Q2
VDDO
Q3
CLK_EN
D
Q
LE
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
LVCMOS_CLK
0
Q0
Q1
Q2
Q3
CLK
nCLK
1
GND
CLK_SEL
ICS8305I
16-LeadTSSOP
4.4mm x 3.0mm x 0.92mm package body
G Package
Top View
OE
8305AGI
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REV. B MAY 19, 2005
1
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 9, 13
GND
Power
Input
Power supply ground.
Output enable. When LOW, outputs are in HIGH impedance state.
When HIGH, outputs are active. LVCMOS / LVTTL interface levels.
2
3
OE
VDD
Pullup
Power
Core supply pin.
Synchronizing clock enable. When LOW, the output clocks are
disabled. When HIGH, output clocks are enabled.
LVCMOS / LVTTL interface levels.
4
CLK_EN
Input
Pullup
5
6
CLK
Input Pulldown Non-inverting differential clock input.
Pullup/
nCLK
Input
Input
Inverting differential clock input. VDD/2 default when left floating.
Pulldown
Pullup
Clock select input. When HIGH, selects CLK, nCLK inputs.
When LOW, selects LVCMOS_CLK input.
LVCMOS / LVTTL interface levels.
7
8
CLK_SEL
LVCMOS_CLK
Input Pulldown LVCMOS / LVTTL clock input.
10, 12, 14, 16 Q3, Q2, Q1, Q0 Output
11, 15 VDDO Power
Clock outputs. LVCMOS / LVTTL interface levels.
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Units
pF
Symbol Parameter
Test Conditions
Minimum Typical Maximum
CIN
Input Capacitance
Input Pullup Resistor
4
RPULLUP
51
51
kΩ
RPULLDOWN Input Pulldown Resistor
kΩ
Power Dissipation Capacitance
(per output)
CPD
11
pF
ROUT
Output Impedance
5
7
12
Ω
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 3A. CONTROL INPUT FUNCTION TABLE
Inputs
CLK_SEL
Outputs
OE
1
CLK_EN
Selected Source
LVCMOS_CLK
CLK, nCLK
Q0:Q3
Disabled; LOW
Disabled; LOW
Enabled
0
0
1
1
X
0
1
0
1
X
1
1
LVCMOS_CLK
CLK, nCLK
1
Enabled
0
HiZ
NOTE: After CLK_EN switches, the clock outputs are disabled or enabled following a rising and falling input clock edge
as shown in Figure 1.
Enabled
Disabled
nCLK
CLK,
LVCMOS_CLK
CLK_EN
Q0:Q3
FIGURE 1. CLK_EN TIMING DIAGRAM
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REV. B MAY 19, 2005
3
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
DD
Inputs, V
-0.5V toVDD + 0.5 V
-0.5V to VDDO + 0.5V
89°C/W (0 lfpm)
-65°C to 150°C
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature,T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
Core Supply Voltage
3.465
3.465
2.625
1.95
21
V
V
3.135
3.3
VDDO
Output Supply Voltage
2.375
2.5
V
1.65
1.8
V
IDD
Power Supply Current
Output Supply Current
mA
mA
IDDO
5
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK_EN, CLK_SEL, OE
LVCMOS_CLK
2
VDD + 0.3
VDD + 0.3
0.8
V
V
Input
VIH
High Voltage
2
CLK_EN, CLK_SEL, OE
LVCMOS_CLK
-0.3
-0.3
V
Input
VIL
Low Voltage
1.3
V
CLK_EN, CLK_SEL, OE
LVCMOS_CLK
VDD = VIN = 3.465V
VDD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
VDDO = 3.3V 5ꢀ
5
µA
µA
µA
µA
V
Input
IIH
High Current
150
CLK_EN, CLK_SEL, OE
LVCMOS_CLK
-150
-5
Input
IIL
Low Current
2.6
VOH
Output High Voltage; NOTE 1
VDDO = 2.5V 5ꢀ
1.8
V
VDDO = 1.8V 0.15V
VDDO - 0.3
V
V
DDO = 3.3V 5ꢀ
0.5
0.5
0.4
V
VOL
Output Low Voltage; NOTE 1
VDDO = 2.5V 5ꢀ
V
VDDO = 1.8V 0.15V
V
IOZL
IOZH
Output Tristate Current Low
Output Tristate Current High
-5
µA
µA
5
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement Information, Output Load Test Circuit.
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REV. B MAY 19, 2005
4
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
IIH Input High Current
Test Conditions
VIN = VDD = 3.465V
VIN = VDD = 3.465V
IN = 0V, VDD = 3.465V
IN = 0V, VDD = 3.465V
Minimum Typical Maximum Units
nCLK
CLK
150
150
µA
µA
µA
µA
V
nCLK
CLK
V
V
-150
-5
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.15
1.3
Common Mode Input Voltage;
NOTE 1, 2
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Ref = CLK/nCLK
Minimum Typical Maximum Units
350
300
MHz
MHz
Ref = LVCMOS_CLK
LVCMOS_CLK;
Propagation Delay, NOTE 1A
tpLH
1.75
2.8
ns
Low to High
CLK, nCLK;
NOTE 1B
tsk(o)
Output Skew; NOTE 2, 6
Measured on the Rising Edge
40
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 6
700
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
tjit
0.04
ps
tR / tF
odc
Output Rise/Fall Time
20ꢀ to 80ꢀ
IJ 200MHz
ƒ> 200MHz
100
45
700
55
58
5
ps
ꢀ
Output Duty Cycle
42
ꢀ
tEN
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
ns
ns
tDIS
5
NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Driving only one input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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REV. B MAY 19, 2005
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Ref = CLK/nCLK
Minimum Typical Maximum Units
350
300
MHz
MHz
Ref = LVCMOS_CLK
LVCMOS_CLK;
Propagation Delay, NOTE 1A
tpLH
1.75
2.95
ns
Low to High
CLK, nCLK;
NOTE 1B
tsk(o)
Output Skew; NOTE 2, 6
Measured on the Rising Edge
40
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 6
800
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
tjit
0.04
ps
tR / tF
odc
Output Rise/Fall Time
20ꢀ to 80ꢀ
IJ 166MHz
f > 166MHz
100
45
700
55
58
5
ps
ꢀ
Output Duty Cycle
42
ꢀ
tEN
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
ns
ns
tDIS
5
NOTE 1A: Measured from the VDD/2 of the input to VDDO/2 of the output.
NOTE 1B: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew between outputs on different devices operating a the same supply voltages and
with equal load conditions. Using the same type of input on each device, the output is measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: Driving only one input clock.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
TABLE 5C. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 1.8V -0.15V, TA = -40°C TO 85°C
Symbol Parameter
fMAX Output Frequency
Test Conditions
Ref = CLK/nCLK
Minimum Typical Maximum Units
350
300
MHz
MHz
Ref = LVCMOS_CLK
LVCMOS_CLK;
Propagation Delay, NOTE 1A
tpLH
1.75
3.7
ns
Low to High
CLK, nCLK;
NOTE 1B
tsk(o)
Output Skew; NOTE 2, 6
Measured on the Rising Edge
45
ps
ps
tsk(pp)
Part-to-Part Skew; NOTE 3, 6
900
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 5
tjit
0.04
ps
tR / tF
odc
Output Rise/Fall Time
20ꢀ to 80ꢀ
IJ 166MHz
f > 166MHz
100
45
700
55
58
5
ps
ꢀ
Output Duty Cycle
42
ꢀ
tEN
Output Enable Time; NOTE 4
Output Disable Time; NOTE 4
ns
ns
tDIS
5
For notes, see Table 5B.
8305AGI
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
Input/Output Additive
Phase Jitter at 155.52MHz
= 0.04ps typical
-10
-20
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
8305AGI
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REV. B MAY 19, 2005
7
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
2.05V 5ꢀ 1.25V 5ꢀ
SCOPE
SCOPE
VDD
VDD
VDDO
,
VDDO
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.4V 0.09V
0.9V 0.075V
VDD
SCOPE
VDD
nCLK
VDDO
VPP
VCMR
Cross Points
Qx
LVCMOS
CLK
GND
GND
-0.9V 0.075V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
Qx
VDDO
2
VDDO
Qx
Qy
2
PART 2
Qy
VDDO
VDDO
2
2
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
VDD
2
LVCMOS_CLK
80ꢀ
tF
80ꢀ
tR
nCLK
CLK
20ꢀ
20ꢀ
Clock
Outputs
VDDO
2
Q0:Q3
➤
tPD
➤
PROPAGATION DELAY
OUTPUT RISE/FALL TIME
VDDO
2
Q0:Q3
tPW
tPERIOD
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV. B MAY 19, 2005
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 2 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1.This bias circuit
should be located as close as possible to the input pin.The ratio
of R1 and R2 might need to be adjusted to position theV_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
V_REF
CLK
nCLK
C1
0.1u
R2
1K
FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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REV. B MAY 19, 2005
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals.BothVSWING and VOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3E show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiver
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
3.3V
3.3V
3.3V
R3
125
R4
125
C1
C2
LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
CLK
nCLK
HiPerClockS
Input
R5
100 - 200
R6
100 - 200
R1
84
R2
84
R5,R6 locate near the driver pin.
FIGURE 3E. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER WITH AC COUPLE
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REV. B MAY 19, 2005
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
SCHEMATIC EXAMPLE
This application note provides general design guide using is driven by an LVCMOS driver. CLK_EN is set at logic low to
ICS8305I LVCMOS buffer. Figure 4 shows a schematic example select LVCMOS_CLK input.
of the ICS8305I LVCMOS clock buffer.In this example, the input
VDD
Zo = 50
VDD
R1
43
R4
1K
R5
1K
U1
1
16
15
14
13
12
11
10
9
GND
OE
VDD
CLK_EN
CLK
nCLK
CLK_SEL
LVCMOS_CLK
Q0
VDDO
Q1
GND
Q2
VDDO
Q3
GND
VDD
2
3
4
5
6
7
8
LVCMOS Receiver
Zo = 50
Zo = 50
R2
43
Ro
~
7
Ohm
R3
43
R6
1K
ICS8305
3,.3V LVCMOS
(U1,3)
(U1,11)
C2
(U1,15)
VDD
C1
0.1u
LVCMOS Receiver
C3
VDD=3.3V
0.1u
0.1u
FIGURE 4. EXAMPLE ICS8305I LVCMOS CLOCK OUTPUT BUFFER SCHEMATIC
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8305I is: 459
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ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 16 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
13
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS8305AGI
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
8305AGI
8305AGI
8305AGIL
8305AGIL
16 Lead TSSOP
ICS8305AGIT
16 Lead TSSOP
2500 tape & reel
tube
ICS8305AGILF
ICS8305AGILFT
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an"LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
14
ICS8305I
LOW SKEW, 1-TO-4, MULTIPLEXED DIFFERENTIAL/
LVCMOS-TO-LVCMOS/LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
Ordering Information table - corrected Part/Order Number typo from
ICS88305AGIT to ICS8305AGIT.
A
T8
14
1/20/04
T5A - T5C
5 & 6
7
AC Characteristics Tables - changed tjit from 0.05ps typical to 0.04ps typical.
Updated Additive Phase Jitter plot.
B
2/26/04
B
B
T1
T8
2
Pin Description Table - corrected CLK_EN description.
Ordering Information Table - added Lead-Free part number
12/7/04
5/19/05
14
8305AGI
www.icst.com/products/hiperclocks.html
REV. B MAY 19, 2005
15
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