ICS8308I [ICSI]
Low Skew, 1-To-8 Differential/LVCOMS-TO-LVCMOS Fanout Buffer; 低偏移， 1至8差分/ LVCOMS - TO- LVCMOS扇出缓冲器
| 型号： | ICS8308I |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | Low Skew, 1-To-8 Differential/LVCOMS-TO-LVCMOS Fanout Buffer |
| 文件： | 总15页 (文件大小：205K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS8308I is a low-skew, 1-to-8 Fanout Buffer
• 8 LVCMOS/LVTTL outputs (7Ω typical output impedance)
and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS.The
ICS8308I has two selectable clock inputs. The
• Selectable LVCMOS_CLK or differential CLK, nCLK
inputs
CLK, nCLK pair can accept most differential input
• CLK, nCLK pair can accept the following differential
levels. The LVCMOS_CLK can accept LVCMOS or LVTTL
input levels. The low impedance LVCMOS/LVTTL outputs
are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased
from 8 to 16 by utilizing the ability of the outputs to drive two
series terminated transmission lines.
input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
• Maximum Output Frequency: 350MHz
• Output Skew: (3.3V 5ꢀ): 100ps (maximum)
• Part to Part Skew: (3.3V 5ꢀ): 1ns (maximum)
• SupplyVoltage Modes:
(Core/Output)
3.3V/3.3V
3.3V/2.5V
2.5V/2.5V
The ICS8308I is characterized for 3.3V core/3.3V output,
3.3V core/2.5V output or 2.5V core/2.5V output operation.
Guaranteed output and part-part skew characteristics make
the 8308I ideal for those clock distribution applications requiring
well defined performance and repeatability.
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free
compliant packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
1
24
23
22
21
20
19
18
17
16
15
14
13
CLK_EN
D
Q0
GND
CLK_SEL
LVCMOS_CLK
CLK
VDDO
Q2
GND
Q3
VDDO
Q4
2
3
4
5
Q
LE
Pullup
LVCMOS_CLK
1
Q0
Pullup
CLK
nCLK
CLK_EN
OE
6
7
8
9
10
11
12
0
Pulldown
nCLK
GND
Q5
VDDO
Q6
GND
Q7
Q1
Q2
Q3
VDD
GND
Q1
VDDO
Pullup
CLK_SEL
Q4
Q5
ICS8308I
24-Lead, 300-MIL TSSOP
4.4mm x 7.8mm x 0.92mm body package
G Package
Q6
Q7
TopView
Pullup
OE
8308AGI
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REV.B JULY 25, 2005
1
ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 11, 13, 15,
17, 19, 21, 23
Q0, Q1, Q7, Q6,
Q5, Q4,Q3, Q2
Output
Power
Clock outputs. LVCMOS / LVTTL interface levels.
2, 10, 14, 18, 22
GND
Power supply ground.
Clock select input. Selects LVCMOS clock input
when HIGH. Selects CLK, nCLK inputs when LOW.
LVCMOS / LVTTL interface levels.
3
CLK_SEL
Input
Pullup
4
LVCMOS_CLK
CLK
Input
Input
Input
Input
Input
Power
Power
Pullup
Pullup
Clock input. LVCMOS / LVTTL interface levels.
Non-inverting differential clock input.
5
6
nCLK
Pulldown Inverting differential clock input.
7
CLK_EN
OE
Pullup
Pullup
Clock enable. LVCMOS / LVTTL interface levels.
8
Output enable. LVCMOS / LVTTL interface levels.
Core supply pin.
9
VDD
12, 16, 20, 24
VDDO
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
12
pF
RPULLUP
Input Pullup Resistor
51
51
7
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
5
12
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock Input
CLK_SEL
0
1
CLK, nCLK is selected
LVCMOS_CLK is selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK_SEL LVCMOS_CLK
CLK
nCLK
Q0:Q7
LOW
HIGH
LOW
HIGH
HIGH
LOW
LOW
HIGH
0
0
0
0
0
0
1
1
—
—
—
—
—
—
0
0
1
Differential to Single Ended
Differential to Single Ended
Non Inverting
Non Inverting
1
0
0
Biased; NOTE 1
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
Biased; NOTE 1
Biased; NOTE 1
0
1
Single Ended to Single Ended
Single Ended to Single Ended
Inverting
Inverting
Biased; NOTE 1
—
—
—
—
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
DD
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
70°C/W (0 lfpm)
-65°C to 150°C
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40° TO 85°
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
46
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
mA
mA
IDDO
11
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
2.375
3.3
2.5
3.465
2.625
46
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
mA
mA
IDDO
10
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD, VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
43
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
mA
mA
IDDO
10
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REV.B JULY 25, 2005
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ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4D. DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40° TO 85°
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS
2
VDD + 0.3
1.3
V
V
LVCMOS_CLK
CLK_EN, OE
-0.3
Input Low Voltage
0.8
0.8
VIN = VDD or
VIN = GND
IIN
Input Current
300
µA
VOH
Output High Voltage; NOTE 1
IOH = -24mA
IOL = 24mA
2.4
V
V
V
V
0.55
0.30
1.3
VOL
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
I
OL = 12mA
VPP
CLK, nCLK
CLK, nCLK
0.15
Input Common Mode Voltage;
NOTE 2, 3
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to VDDO/2.
See Parameter Measurement section, "3.3V Output Load AC Test Circuit".
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 3: Common mode voltage is defined as VIH.
TABLE 4E. DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage
LVCMOS
2
VDD + 0.3
1.3
V
V
V
LVCMOS_CLK
CLK_EN, OE
-0.3
VIL
Input Low Voltage
Input Current
0.8
VIN = VDD or
VIN = GND
IIN
300
µA
VOH
VOL
VPP
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
IOH = -15mA
IOL = 15mA
1.8
V
V
V
0.6
1.3
CLK, nCLK
CLK, nCLK
0.15
Input Common Mode Voltage;
NOTE 2, 3
VCMR
GND + 0.5
VDD - 0.85
V
NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to VDDO/2.
See Parameter Measurement section, "3.3V Output Load AC Test Circuit".
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 3: Common mode voltage is defined as VIH.
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REV.B JULY 25, 2005
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ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4F. DC CHARACTERISTICS, VDD, VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VIH
Input High Voltage
LVCMOS
2
VDD + 0.3
1.3
V
V
V
LVCMOS_CLK
CLK_EN, OE
-0.3
VIL
Input Low Voltage
Input Current
0.7
VIN = VDD or
VIN = GND
IIN
300
µA
VOH
VOL
VPP
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Input Voltage
IOH = -15mA
IOL = 15mA
1.8
V
V
V
0.6
1.3
CLK, nCLK
CLK, nCLK
0.15
Input Common Mode Voltage;
NOTE 2, 3
VCMR
GND + 0.5
V
DD - 0.85
V
NOTE 1: Outputs capable of driving 50Ω transmission lines terminated with 50Ω to VDDO/2.
See Parameter Measurement section, "3.3V Output Load AC Test Circuit".
NOTE 2: For single ended applications, the maximum input voltage for CLK, nCLK is VDD + 0.3V.
NOTE 3: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
350
MHz
CLK, nCLK;
NOTE 1
LVCMOS_CLK;
NOTE 2
IJ 350MHz
IJ 350MHz
2
2
4
ns
Propagation
Delay;
tPD
4
ns
ps
Measured on
rising edge @VDDO/2
tsk(o)
Output Skew; NOTE 3, 7
100
Measured on
rising edge @VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 4, 7
1
ns
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.8V to 2V
0.2
45
1
55
5
ns
ꢀ
IJ 150MHz, Ref = CLK, nCLK
tPZL, tPZH Output Enable Time; NOTE 5
tPLZ, tPHZ Output Disable Time; NOTE 5
ns
ns
5
CLK_EN to
CLK, nCLK
1
0
0
1
ns
ns
ns
ns
Clock Enable
Setup Time;
NOTE 6
tS
CLK_EN to
LVCMOS_CLK
CLK, nCLK to
CLK_EN
LVCMOS_CLK
to CLK_EN
Clock Enable
Hold Time;
NOTE 6
tH
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
350
MHz
CLK, nCLK;
NOTE 1
LVCMOS_CLK;
NOTE 2
IJ 350MHz
IJ 350MHz
2
2
4
ns
Propagation
Delay;
tPD
4
ns
ps
Measured on
rising edge @VDDO/2
tsk(o)
Output Skew; NOTE 3, 7
100
Measured on
rising edge @VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 4, 7
1
ns
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.6V to 1.8V
0.2
45
1.0
55
5
ns
ꢀ
IJ 150MHz, Ref = CLK, nCLK
tPZL, tPZH Output Enable Time; NOTE 5
tPLZ, tPHZ Output Disable Time; NOTE 5
ns
ns
5
CLK_EN to
CLK, nCLK
1
0
0
1
ns
ns
ns
ns
Clock Enable
Setup Time;
NOTE 6
tS
CLK_EN to
LVCMOS_CLK
CLK, nCLK to
CLK_EN
LVCMOS_CLK
to CLK_EN
Clock Enable
Hold Time;
NOTE 6
tH
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
8308AGI
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REV.B JULY 25, 2005
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ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = -40° TO 85°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
350
MHz
CLK, nCLK;
NOTE 1
LVCMOS_CLK;
NOTE 2
IJ 350MHz
IJ 350MHz
1.5
1.7
4.2
ns
Propagation
Delay;
tPD
4.4
ns
ps
Measured on
rising edge @VDDO/2
tsk(o)
Output Skew; NOTE 3, 7
160
Measured on
rising edge @VDDO/2
tsk(pp)
Part-to-Part Skew; NOTE 4, 7
2
ns
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.6V to 1.8V
0.2
40
1.0
60
5
ns
ꢀ
IJ 150MHz, Ref = CLK, nCLK
tPZL, tPZH Output Enable Time; NOTE 5
tPLZ, tPHZ Output Disable Time; NOTE 5
ns
ns
5
CLK_EN to
CLK, nCLK
1
0
0
1
ns
ns
ns
ns
Clock Enable
Setup Time;
NOTE 6
tS
CLK_EN to
LVCMOS_CLK
CLK, nCLK to
CLK_EN
LVCMOS_CLK
to CLK_EN
Clock Enable
Hold Time;
NOTE 6
tH
NOTE 1: Measured from the differential input crossing point to VDDO/2 of the output.
NOTE 2: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages and with
equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: Setup and Hold times are relative to the rising edge of the input clock.
NOTE 7: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
2.05V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
VDD
VDDO
,
VDD
VDDO
Qx
Qx
LVCMOS
GND
LVCMOS
GND
VDDO
2
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5ꢀ
VDD
SCOPE
VDD
VDDO
,
nCLK
VPP
VCMR
Cross Points
Qx
LVCMOS
GND
CLK
GND
-1.25V 5ꢀ
DIFFERENTIAL INPUT LEVEL
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDDO
VDDO
PART 1
Qx
2
Qx
2
PART 2
Qy
VDDO
2
VDDO
Qy
2
tsk(pp)
tsk(o)
OUTPUT SKEW
PART-TO-PART SKEW
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ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
VDDO
2
2V
2V
LVCMOS_
CLK
VDD = VDDO = 3.3V
0.8V
0.8V
nCLK
CLK
Clock
Outputs
tR
tF
VDDO
2
1.8V
tF
Q0:Q7
1.8V
tR
VDD = VDDO = 2.5V or
➤
tPD
➤
V
DD = 3.3V, VDDO = 2.5V
0.6V
0.6V
Clock
Outputs
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
VDDO
2
Q0:Q7
tPW
tPERIOD
tPW
tPERIOD
x 100ꢀ
odc =
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV.B JULY 25, 2005
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ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
CLK
V_REF
nCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CLK INPUT:
LVCMOS OUTPUT:
For applications not requiring the use of the test clock, it can All unused LVCMOS output can be left floating. We
be left floating. Though not required, but for additional recommend that there is no trace attached.
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
but for additional protection, a 1kΩ resistor can be tied from
CLK to ground.
SELECT PINS:
All select pins have internal pull-ups and pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resistor can be used.
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ICS87004I
1:4, DIFFERENTIAL-TO-LVCMOS/LVTTL
ZERO DELAY CLOCK GENERATOR
Integrated
Circuit
Systems, Inc.
DIFFERENTIAL CLOCK INPUT INTERFACE
The CLK /nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL here are examples only. Please consult with the vendor of the
and other differential signals. BothVSWING andVOH must meet the driver component to confirm the driver termination requirements.
VPP and VCMR input requirements. Figures 3A to 3D show inter- For example in Figure 3A, the input termination applies for ICS
face examples for the HiPerClockS CLK/nCLK input driven by HiPerClockS LVHSTL drivers. If you are using an LVHSTL driver
the most common driver types.The input interfaces suggested from another vendor, use their termination recommendation.
3.3V
3.3V
3.3V
1.8V
Zo = 50 Ohm
CLK
Zo = 50 Ohm
CLK
Zo = 50 Ohm
nCLK
Zo = 50 Ohm
HiPerClockS
Input
LVPECL
nCLK
HiPerClockS
Input
LVHSTL
R1
50
R2
50
ICS
HiPerClockS
R1
50
R2
50
LVHSTL Driver
R3
50
FIGURE 3A. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
ICS HIPERCLOCKS LVHSTL DRIVER
FIGURE 3B. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
Zo = 50 Ohm
3.3V
R3
R4
125
125
LVDS_Driver
Zo = 50 Ohm
Zo = 50 Ohm
CLK
CLK
R1
100
nCLK
Receiver
nCLK
HiPerClockS
Input
Zo = 50 Ohm
LVPECL
R1
84
R2
84
FIGURE 3C. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVPECL DRIVER
FIGURE 3D. HIPERCLOCKS CLK/NCLK INPUT DRIVEN BY
3.3V LVDS DRIVER
87004AGI
www.icst.com/products/hiperclocks.html
REV.B JULY 25, 2005
11
ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
SCHEMATIC EXAMPLE
Figure 3 shows a schematic example of the ICS8308I. In this
example, the LVCMOS_CLK input is selected.The decoupling
capacitors should be physically located near the power pin.
VDD
Zo = 50 Ohm
R1
43
R9
1K
R10 R12
VDD
1K
1K
VDD
U1
3.3V LVCMOS/LVTTL
VDD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
16
15
14
13
Q0
GND
VDDO
Q2
GND
Q3
VDDO
Q4
GND
Q5
VDDO
Q6
GND
Q7
Ro
~
7
Ohm
Zo = 50 Ohm
CLK_SEL
LVCMOS_CLK
CLK
nCLK
CLK_EN
OE
VDD
GND
Q1
VDDO
R11 43
3.3V_LVCMOS
9
10
11
12
Zo = 50 Ohm
VDD=3.3V
(U1,16)
(U1,9) VDD (U1,12)
(U1,20)
(U1,24)
R8
43
C1
0.1u
C2
0.1u
C3
0.1u
C4
0.1u
C5
0.1u
ICS8308I
3.3V LVCMOS/LVTTL
FIGURE 3. ICS8308I LVPECL BUFFER SCHEMATIC EXAMPLE
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
63°C/W
60°C/W
TRANSISTOR COUNT
The transistor count for ICS8308I is: 1040
8308AGI
www.icst.com/products/hiperclocks.html
REV.B JULY 25, 2005
12
ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
REFERENCE DOCUMENT:JEDEC PUBLICATION 95, MO-153
8308AGI
www.icst.com/products/hiperclocks.html
REV.B JULY 25, 2005
13
ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS8308AGI
ICS8308AGIT
ICS8308AGILF
ICS8308AGILFT
ICS8308AGI
ICS8308AGI
24 Lead TSSOP
24 Lead TSSOP
tape & reel
tube
ICS8308AGILF
ICS8308AGILF
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuraiton and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
8308AGI
www.icst.com/products/hiperclocks.html
REV.B JULY 25, 2005
14
ICS8308I
LOW SKEW, 1-TO-8
DIFFERENTIAL/LVCMOS-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
A
11
Added Schematic Layout
4/16/04
1
3
4
6
8
Features section - added mix supply voltage bullet.
Added Mix Power Supply Table.
Added Mix DC Characteristics Table.
Added Mix AC Characteristics Table.
Added Mix Output Load AC Test Circuit Diagram.
T4B
T4E
T5B
B
10/20/04
B
B
T8
T8
14
Ordering Information Table - added "Lead-Free" part number.
1/12/05
7/25/05
1
10
14
Corrected Block Diagram, added CLK_SEL.
Added "Recommendations for Unused Input and Output Pins".
Ordering Information Table - added Lead-Free note.
8308AGI
www.icst.com/products/hiperclocks.html
REV.B JULY 25, 2005
15
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