ICS83115BRLF [ICSI]
LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER; 低偏移， 1至16 LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS83115BRLF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-16 LVCMOS / LVTTL FANOUT BUFFER |
| 文件： | 总9页 (文件大小：180K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83115
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83115 is a low skew, 1-to-16 LVCMOS/
• 16 LVCMOS/LVTTL outputs
ICS
LVTTL Fanout Buffer and a member of the
HiPerClockS™ family of High Performance Clock
Solutions from ICS.The ICS83115 single ended
clock input accepts LVCMOS or LVTTL input lev-
• 1 LVCMOS/LVTTL clock input
• Maximum output frequency: 200MHz
• All inputs are 5V tolerant
HiPerClockS™
els.The ICS83115 operates at full 3.3V supply mode over the
commercial temperature range.Guaranteed output and part-to-
part skew characteristics make the ICS83115 ideal for those
clock distribution applications demanding well defined perfor-
mance and repeatability.
• Output skew: 250ps (maximum)
• Part-to-part skew: 800ps (maximum)
• Additive phase jitter, RMS: 0.09ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
VDD
OE2
4
OE1
Q0
Q1
1
2
3
4
5
6
7
8
28
27
26
25
24
23
22
21
20
19
18
17
16
15
OE2
Q15
Q14
Q13
VDD
IN
Q2
VDD
VDD
Q3
VDD
Q0
Q1
Q15
Q14
Q13
Q12
Q12
Q11
GND
GND
Q10
Q9
Q4
GND
GND
Q5
Q6
Q7
9
10
11
12
13
14
Q2
Q3
Q8
OE0
IN
Q4
Q5
Q6
Q11
Q10
Q9
ICS83115
28-Lead SSOP, 150mil
9.9mm x 3.9mm x 1.7mm body package
R Package
Q7
Q8
(TopView)
4
OE1
GND
OE0
83115BR
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REV. A SEPTEMBER 21, 2004
1
ICS83115
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Description
Number
1
Name
OE1
Type
Pullup
Output enable. When LOW, forces outputs Q2 thru Q7 to HiZ state.
5V tolerant. LVCMOS/LVTTL interface levels.
Input
2, 3, 4, 7,
Q0, Q1, Q2, Q3,
8, 11, 12, 13, Q4, Q5, Q6, Q7,
16, 17, 18,
21, 22, 25,
26, 27
Q8, Q9, Q10,
Q11, Q12, Q13,
Q14, Q15
Output
LVCMOS/LVTTL clock outputs. 7Ω typical output impedance.
5, 6, 23, 24
9, 10, 19, 20
14
VDD
GND
IN
Power
Power
Input
Core supply pin.
Power supply ground.
Pulldown LVCMOS/LVTTL clock input / 5V tolerant.
Output enable. When LOW, forces outputs Q8 thru Q13 to
HiZ state. 5V tolerant. LVCMOS/LVTTL interface levels.
Output enable. When LOW, forces outputs Q0, Q1, Q15 and Q14 to
HiZ state. 5V tolerant. LVCMOS/LVTTL interface levels.
15
28
OE0
OE2
Input
Input
Pullup
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
VDD = 3.465V
11
pF
RPULLUP
Input Pullup Resistor
51
51
7
KΩ
KΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
VDD = 3.3V
5
12
TABLE 3. FUNCTION TABLE
Inputs
Outputs
Q2:Q7
(Control OE1) (Control OE0)
Q0, Q1, Q14, Q15
(Control OE2)
Q8:Q13
OE0
OE1
OE2
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
HiZ
Active
HiZ
HiZ
HiZ
HiZ
HiZ
Active
Active
HiZ
HiZ
Active
HiZ
HiZ
Active
Active
Active
Active
Active
HiZ
HiZ
Active
Active
Active
NOTE: OE0:OE2 are 5V tolerant.
83115BR
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REV. A SEPTEMBER 21, 2004
2
ICS83115
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDD + 0.5V
49°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0° TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
IDD
Power Supply Voltage
Power Supply Current
3.135
3.3
3.465
50
V
mA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0° TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
OE0:OE2
IN
2
V
V
DD + 0.3
DD + 0.3
0.8
V
V
VIH
VIL
IIH
Input High Voltage
2
OE0:OE2
IN
-0.3
-0.3
V
Input Low Voltage
Input High Current
Input Low Current
1.3
V
OE0:OE2
IN
VDD = VIN = 3.465V
5
µA
µA
µA
µA
V
V
DD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
150
OE0:OE2
IN
-150
-5
IIL
V
VOH
VOL
IOZL
IOZH
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Output HiZ Current Low
2.6
0.5
5
V
µA
µA
Output HiZ Current High
5
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
83115BR
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REV. A SEPTEMBER 21, 2004
3
ICS83115
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = 0° TO 70°C
Symbol Parameter
fMAX Output Frequency
tpLH
Test Conditions
Minimum Typical Maximum Units
200
3.1
MHz
ns
Propagation Delay; NOTE 1
IJ 200MHz
1.7
2.4
0.09
150
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter
Section
Integration Range:
12KHz - 20MHz
tjit(Ø)
ps
tsk(o)
tsk(pp)
tR / tF
odc
Output Skew; NOTE 2, 4
Part-to-Part Skew; NOTE 3, 4
Output Rise/Fall Time
Output Duty Cycle
Measured on rising edge @VDD/2
Measured on rising edge @VDD/2
20ꢀ to 80ꢀ
250
800
1150
55
ps
ps
ps
ꢀ
650
45
tEN
Output Enable Time
20
ns
ns
tDIS
Output Disable Time
20
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDD/2.
NOTE 3: Defined as skew between outputs on different devices operating at the same supply voltages and with equal load
conditions. Using the same type of inputs on each device, the outputs are measured at VDD/2.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
83115BR
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REV. A SEPTEMBER 21, 2004
4
ICS83115
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
-30
Additive Phase Jitter, RMS
@ 155.52MHz (12KHz to 20MHz)
= 0.09ps typical
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
83115BR
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REV. A SEPTEMBER 21, 2004
5
ICS83115
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
VDD
2
SCOPE
VDD
Qx
Qy
Qx
LVCMOS
VDD
2
GND
tsk(b)
-1.65V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Part 1
Qx
VDD
2
VDD
2
CLK
Part 2
Qy
VDD
VDD
2
Q0:Q15
t
2
tsk(pp)
PD
PROPAGATION DELAY
PART-TO-PART SKEW
VDD
2
80ꢀ
tF
80ꢀ
tR
Q0:Q15
Pulse Width
20ꢀ
20ꢀ
tPERIOD
Clock
Outputs
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
83115BR
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REV. A SEPTEMBER 21, 2004
6
ICS83115
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 28 LEAD SSOP, 150MIL
θJA by Velocity (Linear Feet per Minute)
0
200
36°C/W
500
30°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
49°C/W
NOTE: Most modern PCB designs use multi-layered boards.
TRANSISTOR COUNT
The transistor count for ICS83115 is: 985
83115BR
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REV. A SEPTEMBER 21, 2004
7
ICS83115
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
PACKAGE OUTLINE - R SUFFIX FOR 28 LEAD SSOP, 150 MIL
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
28
1.35
0.10
1.75
0.25
1.50
0.30
0.25
10.00
6.20
4.00
A1
A2
b
0.20
0.18
9.80
5.80
3.80
c
D
E
E1
e
0.635 BASIC
0.84 REF
L
0.40
0°
1.27
8°
α
ZD
Reference Document: JEDEC Publication 95, MO-137
83115BR
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REV. A SEPTEMBER 21, 2004
8
ICS83115
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-16
LVCMOS / LVTTL FANOUT
BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS83115BR
Marking
Package
28 Lead SSOP
Count
48 per tube
2500
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS83115BR
ICS83115BR
ICS83115BRT
28 Lead SSOP on Tape and Reel
28 Lead "Lead Free" SSOP
28 Lead "Lead Free" SSOP on Tape and Reel
ICS83115BRLF
ICS83115BRLFT
ICS83115BRLF
ICS83115BRLF
48 per tube
2500
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
83115BR
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REV. A SEPTEMBER 21, 2004
9
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