ICS8312AYIT [ICSI]
LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER; 低偏移， 1到12 LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS8312AYIT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-12 LVCMOS / LVTTL FANOUT BUFFER |
| 文件： | 总11页 (文件大小：243K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8312I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS8312I is a low skew, 1-to-12 LVCMOS /
• 12 LVCMOS / LVTTL outputs
• LVCMOS / LVTTL clock input
• Maximum output frequency: 250MHz
• Output skew: 160ps (maximum)
ICS
LVTTL Fanout Buffer and a member of the
HiPerClockS™family of High Performance Clock
Solutions from ICS.The ICS8312I single ended
clock input accepts LVCMOS or LVTTL input lev-
HiPerClockS™
els. The low impedance LVCMOS outputs are designed to
drive 50Ω series or parallel terminated transmission lines.The
effective fanout can be increased from 12 to 24 by utilizing
the ability of the outputs to drive two series terminated lines.
• Operating supply modes: Core/Output
3.3V/3.3V
2.5V/2.5V
1.8V/1.8V
3.3V/2.5V
3.3V/1.8V
2.5V/1.8V
The ICS8312I is characterized at full 3.3V, 2.5V, and 1.8V, or
mixed 3.3V core/2.5V, 3.3V core/1.8V and 2.5V core/1.8V out-
put operating supply modes. Guaranteed output and part-to-
part skew characteristics along with the 1.8V output capa-
bilities makes the ICS8312I ideal for high performance, single
ended applications that also require a limited output voltage.
• -40°C to 85°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
nD
LE
CLK_EN
CLK
Q
GND
VDD
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q4
VDDO
Q5
12
CLK_EN
CLK
Q0:Q11
GND
Q6
ICS8312I
GND
OE
VDDO
Q7
VDD
GND
GND
9
10 11 12 13 14 15 16
OE
32-Lead LQFP
7mm x 7mm x 1.4mm body package
Y Pacakge
TopView
8312AYI
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REV. A OCTOBER 23, 2003
1
ICS8312I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 5, 8, 12,
16, 17, 21,
25, 29
GND
Power
Power supply ground.
2, 7
VDD
CLK_EN
CLK
Power
Input
Input
Input
Core supply pins.
Synchronous control for enabling and disabling clock outputs.
LVCMOS / LVTTL interface levels.
3
Pullup
4
Pulldown Clock input. LVCMOS / LVTTL interface levels.
Output enable. Controls enabling and disabling of outputs
Q0 thru Q11. LVCMOS / LVTTL interface levels.
6
OE
Pullup
9, 11, 13, 15,
18, 20, 22,
24, 26, 28,
30, 32
Q11, Q10, Q9, Q8,
Q7, Q6, Q5,
Q4, Q3, Q2,
Q1, Q0
Output
Q0 thru Q11 outputs. LVCMOS / LVTTL interface levels.
10, 14, 19,
23, 27, 31
VDDO
Power
Output supply pins.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
pF
pF
pF
KΩ
KΩ
Ω
VDDO = 3.465V
VDDO = 2.625V
VDDO = 2V
19
18
16
Power Dissipation Capacitance
(per output)
CPD
RPULLUP
Input Pullup Resistor
51
51
7
RPULLDOWN Input Pulldown Resistor
VDDO = 3.3V 5%
VDDO = 2.5V 5%
VDDO = 1.8V 0.2V
ROUT
Output Impedance
7
Ω
10
Ω
TABLE 3A. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Control Inputs
Output
Q0:Q11
OE
CLK_EN
0
1
1
X
0
1
Hi-Z
LOW
Follows CLK input
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Q0:Q11
LOW
OE
1
CLK_EN
CLK
1
1
0
1
1
HIGH
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REV. A OCTOBER 23, 2003
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ICS8312I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
SupplyVoltage, V
4.6V
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
I
Outputs, VO
PackageThermal Impedance, θJA 47.9°C/W (0 lfpm)
StorageTemperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
10
V
V
Output Supply Voltage
Power Supply Current
Output Supply Current
µA
µA
IDDO
10
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
10
V
V
Output Supply Voltage
Power Supply Current
Output Supply Current
µA
µA
IDDO
10
TABLE 4C. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
1.6
1.6
1.8
1.8
2.0
2.0
10
V
V
Output Supply Voltage
Power Supply Current
Output Supply Current
µA
µA
IDDO
10
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
2.375
3.3
2.5
3.465
2.625
10
V
V
Output Supply Voltage
Power Supply Current
Output Supply Current
µA
µA
IDDO
10
TABLE 4E. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
1.6
3.3
1.8
3.465
2.0
V
Output Supply Voltage
Power Supply Current
Output Supply Current
V
10
µA
µA
IDDO
10
TABLE 4F. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
2.375
1.6
2.5
1.8
2.625
2.0
V
V
Output Supply Voltage
Power Supply Current
Output Supply Current
10
µA
µA
IDDO
10
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ICS8312I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 4F. LVCMOS/LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
DD = 3.3V 5%
Minimum Typical Maximum Units
V
2
1.7
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
VDD + 0.3
1.3
V
V
CLK
VDD = 2.5V 5%
VDD = 1.8V 0.2V
0.65*VDD
2
V
VIH
VIL
IIH
Input High Voltage
VDD = 3.3V 5%
V
CLK_EN, OE
CLK
VDD = 2.5V 5%
VDD = 1.8V 0.2V
1.7
V
0.65*VDD
-0.3
V
VDD = 3.3V 5%
V
VDD = 2.5V 5%
VDD = 1.8V 0.2V
-0.3
0.7
V
-0.3
0.35*VDD
1.3
V
Input Low Voltage
Input High Current
Input Low Current
VDD = 3.3V 5%
-0.3
V
CLK_EN, OE
CLK
VDD = 2.5V 5%
VDD = 1.8V 0.2V
-0.3
0.7
V
-0.3
0.35*VDD
150
V
V
DD = 3.3V 5%
DD = 2.5V 5%
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
µA
V
V
150
V
DD = 1.8V 0.2V
150
VDD = 3.3V 5%
VDD = 2.5V 5%
5
CLK_EN, OE
CLK
5
V
DD = 1.8V 0.2V
5
VDD = 3.3V 5%
-5
-5
VDD = 2.5V 5%
VDD = 1.8V 0.2V
-5
IIL
V
DD = 3.3V 5%
DD = 2.5V 5%
DD = 1.8V 0.2V
-150
-150
-150
2.6
2
CLK_EN, OE
V
V
VDDO = 3.3V 5%; NOTE 1
VDDO = 2.5V 5%; IOH = -1mA
VDDO = 2.5V 5%; NOTE 1
V
VOH
Output High Voltage
Output Low Voltage
1.8
V
VDDO = 1.8V 0.2V; IOH = -100uA VDD - 0.2
V
VDDO = 1.8V 0.2V; NOTE 1
VDDO = 3.3V 5%; NOTE 1
VDDO = 2.5V 5%; IOL = 1mA
VDDO = 2.5V 5%; NOTE 1
VDDO = 1.8V 0.2V; IOL = 100uA
VDDO = 1.8V 0.2V; NOTE 1
VDD - 0.3
V
0.5
0.4
V
V
VOL
0.45
0.2
V
V
0.35
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagrams.
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REV. A OCTOBER 23, 2003
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ICS8312I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
250
2.7
150
850
800
55
MHz
ns
tpLH
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 250MHz
1.2
2.0
tsk(o)
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
ps
tR/tF
odc
Output Rise Time; NOTE 4
Output Duty Cycle
20% to 80%
175
45
ps
f ≤ 150MHz
%
All parameters measured at fMAX unless noted otherwise.
See Table 5C listed below for Notes 1 through 5.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
250
3.5
155
1.1
800
55
MHz
ns
tpLH
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 250MHz
1.25
2.4
tsk(o)
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
ns
tR/tF
odc
Output Rise Time; NOTE 4
Output Duty Cycle
20% to 80%
200
45
ps
f ≤ 150MHz
%
All parameters measured at fMAX unless noted otherwise.
See Table 5C listed below for Notes 1 through
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
200
4.9
160
2.4
875
55
MHz
ns
tpLH
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 200MHz
1.6
3.3
tsk(o)
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
ns
tR/tF
odc
Output Rise Time; NOTE 4
Output Duty Cycle
20% to 80%
175
45
ps
f ≤ 100MHz
%
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A OCTOBER 23, 2003
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ICS8312I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 5D. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
250
2.8
150
1
MHz
ns
tpLH
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 250MHz
1.5
2.1
tsk(o)
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
ns
tR/tF
odc
Output Rise Time; NOTE 4
Output Duty Cycle
20% to 80%
200
45
800
55
ps
f ≤ 150MHz
%
All parameters measured at fMAX unless noted otherwise.
See Table 5F listed below for Notes 1 through 5.
TABLE 5E. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
200
3.5
150
1.4
800
55
MHz
ns
tpLH
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 200MHz
1.5
2.5
tsk(o)
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
ns
tR/tF
odc
Output Rise Time; NOTE 4
Output Duty Cycle
20% to 80%
200
45
ps
f ≤ 100MHz
%
All parameters measured at fMAX unless noted otherwise.
See Table 5F listed below for Notes 1 through
TABLE 5F. AC CHARACTERISTICS, VDD = 2.5V 5%, VDDO = 1.8V 0.2V, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
200
3.9
160
1.6
800
55
MHz
ns
tpLH
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
f ≤ 200MHz
1.4
2.7
tsk(o)
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
ns
tR/tF
odc
Output Rise Time; NOTE 4
Output Duty Cycle
20% to 80%
200
45
ps
f ≤ 100MHz
%
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
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ICS8312I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V 5%
1.25V 5%
SCOPE
SCOPE
VDD
VDDO
,
VDD
VDDO
,
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.165V 5%
-1.25V 5%
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V 5% 1.25V 5%
0.9V 0.1V
SCOPE
VDD
SCOPE
VDD
VDDO
,
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-0.9V 0.1V
-1.25V 5%
1.8V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
2.05V 5%
2.4 0.9V
0.9V 0.1V
0.9V 0.1V
SCOPE
SCOPE
VDD
VDD
VDDO
VDDO
Qx
Qx
LVCMOS
LVCMOS
GND
GND
-0.9V 0.1V
-0.9V 0.1V
3.3V CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
2.5 CORE/1.8V OUTPUT LOAD AC TEST CIRCUIT
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REV. A OCTOBER 23, 2003
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ICS8312I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
Part 1
Qx
VDDO
VDDO
2
Qx
Qy
2
Part 2
Qy
VDDO
2
VDDO
2
tsk(o)
tsk(pp)
OUTPUT SKEW
PART-TO-PART SKEW
VDD
80%
tF
80%
2
CLK
20%
20%
Clock
VDDO
tR
Outputs
2
Q0:Q11
t
PD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
VDDO
2
Q0:Q11
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
8312AYI
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REV. A OCTOBER 23, 2003
8
ICS8312I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8312I is: 339
8312AYI
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REV. A OCTOBER 23, 2003
9
ICS8312I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
http://www.icst.com/products/hiperclocks.html
8312AYI
REV. A OCTOBER 23, 2003
10
ICS8312I
LOW SKEW, 1-TO-12
LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS8312AYI
Marking
Package
32 Lead LQFP
Count
250 per tray -40°C to 85°C
1000 -40°C to 85°C
Temperature
ICS8312AYI
ICS8312AYI
ICS8312AYIT
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV. A OCTOBER 23, 2003
11
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