ICS8316AKLF [ICSI]
LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS; 低偏移， 1 - TO- 16 ， LVCMOS / LVTTL扇出缓冲器W / 1.2V LVCMOS输出
| 型号： | ICS8316AKLF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-16, LVCMOS / LVTTL FANOUT BUFFER W/1.2V LVCMOS OUTPUTS |
| 文件： | 总7页 (文件大小：148K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8316
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16, LVCMOS / LVTTL
FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
GENERAL DESCRIPTION
FEATURES
The ICS8316 is a low skew, 1-to-16 LVCMOS/
• Sixteen 1.2V LVCMOS / LVTTL outputs
ICS
HiPerClockS™
LVTTL Fanout Buffer with 1.2V LVCMOS Outputs
and a member of the HiPerClockS™ family of
High Performance Clock Solutions from ICS.The
ICS8316 single ended clock input accepts
• LVCMOS / LVTTL clock input
• Maximum output frequency: 150MHz
• Output skew: TBD
LVCMOS or LVTTL input levels.The low impedance LVCMOS
outputs are designed to drive 50Ω series or parallel termi-
nated transmission lines.
• Propagation delay: 3.5ns (typical)
• 3.3V core/1.2V output operating supply mode
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
Guaranteed output and part-to-part skew characteristics
along with the 1.2V output makes the ICS8316 ideal for high
performance, single ended applications that also require a
limited output voltage.
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
32 31 30 29 28 27 26 25
CLK
1
2
3
4
5
6
7
8
24
VDDO
QA0
QA1
QA2
QA3
GND
OEA
CLK
VDDO
QC0
QC1
QC2
QC3
GND
OEC
GND
23
22
21
20
19
18
4
QA0:QA3
OEA
ICS8316
4
QB0:QB3
OEB
4
QC0:QC3
17
OEC
9
10 11 12 13 14 15 16
4
QD0:QD3
OED
32-LeadVFQFN
5mm x 5mm x 0.95 package body
K Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
8316AK
http://www.icst.com/products/hiperclocks.html
REV.A DECEMBER 22, 2005
1
PRELIMINARY
ICS8316
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16, LVCMOS / LVTTL
FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
TABLE 1. PIN DESCRIPTIONS
Number
1, 16, 24, 25
2, 3, 4, 5
6, 11, 17,
19, 30, 32
Name
VDDO
QA0, QA1, QA2, QA3 Output
Type
Description
Power
Output supply pins.
Bank A clock outputs. LVCMOS / LVTTL interface levels.
Power supply ground.
GND
OEA
Power
Input
Bank A output enable pin. Controls enabling and disabling
of QA0:QA3 outputs. LVCMOS / LVTTL interface levels.
7
Pullup
8
9
CLK
VDD
Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
Power
Input
Core supply pin.
Bank B output enable pin. Controls enabling and disabling
of QB0:QB3 outputs. LVCMOS / LVTTL interface levels.
10
12, 13, 14, 15
18
OEB
Pullup
Pullup
QB3, QB2, QB1, QB0 Output
OEC Input
Bank B clock outputs. LVCMOS / LVTTL interface levels.
Bank C output enable pin. Controls enabling and disabling
of QC0:QC3 outputs. LVCMOS / LVTTL interface levels.
20, 21, 22, 23
26, 27, 28, 29
QC3, QC2, QC1, QC0 Output
QD0, QD1, QD2, QD3 Output
Bank C clock outputs. LVCMOS / LVTTL interface levels.
Bank D clock outputs. LVCMOS / LVTTL interface levels.
Bank D output enable pin. Controls enabling and disabling
of QD0:QD3 outputs. LVCMOS / LVTTL interface levels.
31
OED
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
V
DDO = 1.26V
TBD
pF
RPULLUP
Input Pullup Resistor
51
51
15
kΩ
kΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
VDDO = 1.2 5%
TABLE 3A. OUTPUT ENABLE AND CLOCK ENABLE FUNCTION TABLE
Control Inputs
Outputs
Qx0:Qx3
Hi-Z
OE[A:D]
0
1
Active
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
OE[A:D]
CLK
Qx0:Qx3
LOW
1
1
0
1
HIGH
8316AK
http://www.icst.com/products/hiperclocks.html
REV.A DECEMBER 22, 2005
2
PRELIMINARY
ICS8316
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16, LVCMOS / LVTTL
FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
ABSOLUTE MAXIMUM RATINGS
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
SupplyVoltage, V
4.6V
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO + 0.5V
I
Outputs, VO
PackageThermal Impedance, θJA 34.8°C/W (0 lfpm)
StorageTemperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V, VDDO = 1.2V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Core Supply Voltage
3.135
1.14
3.3
1.2
3.465
1.26
V
V
Output Supply Voltage
Power Supply Current
Output Supply Current
TBD
TBD
µA
µA
IDDO
TABLE 4B. LVCMOS DC CHARACTERISTICS, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
V
V
Input Low Voltage
-0.3
0.8
150
5
CLK
V
DD = VIN = 3.465V
DD = VIN = 3.465V
µA
µA
µA
µA
V
IIH
Input High Current
OEA:OED
CLK
V
V
DD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-5
IIL
Input Low Current
OEA:OED
V
-150
VOH
VOL
Output High Voltage
Output Low Voltage
VDDO = 1.2V 5%; NOTE 1
VDDO = 1.2V 5%; NOTE 1
VDD*0.7
VDD*0.3
V
NOTE 1: Outputs terminated with 50Ω to VDDO/2. See Parameter Measurement section, "Load Test Circuit" diagram.
TABLE 5. AC CHARACTERISTICS, VDD = 3.3V 5%, VDDO = 1.2V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fMAX
Output Frequency
150
MHz
ns
tpLH
Propagation Delay Low to High; NOTE 1
Output Skew; NOTE 2, 5
3.5
TBD
TBD
650
50
tsk(o)
ps
tsk(pp) Part-to-Part Skew; NOTE 3, 5
ps
tR/tF
odc
Output Rise Time; NOTE 4
Output Duty Cycle
20% to 80%
ps
%
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as the skew between outputs on different devices operating at the same supply voltages and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 4: These parameters are guaranteed by characterization. Not tested in production.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
8316AK
http://www.icst.com/products/hiperclocks.html
REV.A DECEMBER 22, 2005
3
PRELIMINARY
ICS8316
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16, LVCMOS / LVTTL
FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
PARAMETER MEASUREMENT INFORMATION
2.7V 5%
0.6V 5%
VDDO
2
SCOPE
VDD
Qx
Qy
VDDO
Qx
LVCMOS
VDDO
GND
2
tsk(o)
-0.6V 5%
3.3V CORE/1.2V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Part 1
Qx
VDDO
2
VDDO
2
Qx0:Qx3
Qx0:Qx3
VDDO
Part 2
Qy
VDDO
2
2
tsk(pp)
tsk(b)
PART-TO-PART SKEW
BANK SKEW (where x denotes outputs in the same bank)
QA0:QA3,
VDDO
2
QB0:QB3,
QC0:QC3,
QD0:QD3
VDD
2
CLK
tPW
tPERIOD
VDDO
2
QA0:QA3,
QB0:QB3,
QC0:QC3,
QD0:QD3
t
tPW
PD
x 100%
odc =
tPERIOD
PROPAGATION DELAY
OUTPUT DUTY CYCLE/PLUSE WIDTH/PERIOD
80%
tF
80%
tR
20%
20%
Clock
Outputs
OUTPUT RISE/FALL TIME
8316AK
http://www.icst.com/products/hiperclocks.html
REV.A DECEMBER 22, 2005
4
PRELIMINARY
ICS8316
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16, LVCMOS / LVTTL
FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
LVCMOS CONTROL PINS:
OUTPUTS:
LVCMOS OUTPUT:
All control pins have internal pull-ups or pull-downs; additional All unused LVCMOS output can be left floating. We
resistance is not required but can be added for additional recommend that there is no trace attached.
protection. A 1kΩ resistor can be used.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD VFQFN
θJA vs. 0 Air Flow (Linear Feet per Minute)
0
Multi-Layer PCB, JEDEC Standard Test Boards
34.8°C/W
TRANSISTOR COUNT
The transistor count for ICS8316 is: 416
8316AK
http://www.icst.com/products/hiperclocks.html
REV.A DECEMBER 22, 2005
5
PRELIMINARY
ICS8316
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16, LVCMOS / LVTTL
FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
PACKAGE OUTLINE AND DIMENSIONS - K SUFFIX FOR 32 LEAD VFQFN
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
VHHD-2
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
0.80
0
1.00
0.05
A1
A3
b
--
0.25 Ref.
0.25
0.18
0.30
8
ND
NE
D
8
5.00 BASIC
2.25
D2
E
1.25
1.25
0.30
3.25
3.25
0.50
5.00 BASIC
2.25
E2
e
0.50 BASIC
0.40
L
Reference Document: JEDEC Publication 95, MO-220
8316AK
http://www.icst.com/products/hiperclocks.html
REV.A DECEMBER 22, 2005
6
PRELIMINARY
ICS8316
Integrated
Circuit
Systems, Inc.
LOW SKEW, 1-TO-16, LVCMOS / LVTTL
FANOUT BUFFER W/1.2V LVCMOS OUTPUTS
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS8316AK
Marking
Package
Shipping Packaging
tray
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS8316AK
ICS8316AK
TBD
32 Lead VFQFN
ICS8316AKT
32 Lead VFQFN
2500 tape & reel
tray
ICS8316AKLF
ICS8316AKLFT
32 Lead "Lead-Free" VFQFN
32 Lead "Lead-Free" VFQFN
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8316AK
http://www.icst.com/products/hiperclocks.html
REV.A DECEMBER 22, 2005
7
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