ICS8344AY-01T [ICSI]
LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER; 低偏移， 1至24差分至LVCMOS扇出缓冲器
| 型号： | ICS8344AY-01T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-24 DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER |
| 文件： | 总16页 (文件大小：142K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS8344-01
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS8344-01 is a low voltage, low skew • 24 LVCMOS outputs, 7Ω typical output impedance
fanout buffer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
• 2 selectable CLKx, nCLKx inputs
HiPerClockS™
ICS. The ICS8344-01 has two selectable clock
inputs. The CLK0, nCLK0 and CLK1, nCLK1 pairs
• CLK0, nCLK0 and CLK1, nCLK1 pairs can accept the
following input levels: LVDS, LVPECL, LVHSTL, SSTL,
HCSL
can accept most standard differential input levels. The
ICS8344-01 is designed to translate any differential signal
levels to LVCMOS levels. The low impedance LVCMOS out-
puts are designed to drive 50Ω series or parallel terminated
transmission lines. The effective fanout can be increased to
48 by utilizing the ability of the outputs to drive two series
terminated lines. Redundant clock applications can make use
of the dual clock input. The dual clock inputs also facilitate
board level testing. The clock enable is internally synchro-
nized to eliminate runt pulses on the outputs during asyn-
chronous assertion/deassertion of the clock enable pin. The
outputs are driven low when disabled. The ICS8344-01 is
characterized at full 3.3V, full 2.5V and mixed 3.3V input and
2.5V output operating supply modes.
• Output frequency up to 250MHz
• Translates any single ended input signal to LVCMOS with
resistor bias on nCLK input
• Synchronous clock enable
• Output skew: 200 ps (maximum)
• Part-to-part skew: 900ps (maximum)
• Bank skew: 85ps (maximum)
• Propagation delay: 5ns (maximum)
• 3.3V, 2.5V or mixed 3.3V, 2.5V operating supply modes
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
Guaranteed output and part-to-part skew characteristics
make the ICS8344-01 ideal for those clock distribution
applications demanding well defined performance and
repeatability.
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
CLK0
nCLK0
1
48 47 46 45 44 43 42 41 40 39 38 37
Q16
Q17
VDDO
GND
Q18
Q19
Q20
Q21
VDDO
GND
Q22
Q23
1
36
35
34
33
32
31
30
29
28
27
26
25
Q7
CLK1
nCLK1
0
2
Q6
3
VDDO
GND
Q5
Q0 - Q7
4
5
6
Q4
Q8 - Q15
Q16 - Q23
ICS8344-01
7
Q3
8
Q2
9
VDDO
GND
Q1
10
11
12
LE
nD
Q0
13 14 15 16 17 18 19 20 21 22 23 24
Q
CLK_EN
OE
48-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
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ICS8344-01
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 5, 6
7, 8, 11, 12
Q16, Q17, Q18, Q19
Q20, Q21, Q22, Q23
Output
Q16 thru Q23 outputs. 7Ω typical output impedance.
3, 9, 28,
34, 39, 45
4, 10, 14,18,
27, 33, 40, 46
VDDO
Power
Power
Output supply pins. Connect 3.3V or 2.5V.
GND
Power supply ground. Connect to ground.
Clock select input. When HIGH, selects CLK1, nCLK inputs,
13
CLK_SEL
Input
Pulldown When LOW, selects CLK0, nCLK0 inputs.
LVCMOS / LVTTL interface levelss.
15, 19
16
VDD
Power
Input
Input
Input
Input
Positive supply pins. Connect 3.3V or 2.5V.
nCLK1
CLK1
nCLK0
CLK0
Pullup
Pulldown Non-inverting differential LVPECL clock input.
Pullup Inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
17
20
21
Pulldown Non-inverting differential LVPECL clock input.
Synchronizing control for enabling and disabling clock outputs.
LVCMOS interface levels.
22
CLK_EN
Input
Pullup
Output enable. Controls enabling and disabling of outputs
Q0 thru Q23.
23
24
OE
nc
Input
Unused
Output
Pullup
No connect.
25, 26, 29, 30
31, 32, 35, 36
37, 38, 41, 42
Q0, Q1, Q2, Q3
Q4, Q5, Q6, Q7
Q8, Q9, Q10, Q11
Q0 thru Q7 outputs. 7Ω typical output impedance.
Output
Q8 thru Q15 outputs. 7Ω typical output impedance.
43, 44, 47, 48 Q12, Q13, Q14, Q15
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CLK0, nCLK0,
CLK1, nCLK1
CLK-SEL,
4
4
pF
pF
CIN
Input Capacitance
CLK_EN, OE
pF
pF
pF
KΩ
KΩ
Ω
Power Dissipation Capacitance
(per output)
CPD
RPULLUP
RPULLDOWN
ROUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
51
51
7
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ICS8344-01
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 3A. OUPUT ENABLE FUNCTION TABLE
Bank 1
Bank 2
Bank 3
Input
OE
0
Output
Q0-Q7
Hi-Z
Input
OE
0
Output
Q8-Q15
Hi-Z
Input
OE
0
Output
Q16-Q23
Hi-Z
1
Enabled
1
Enabled
1
Enabled
TABLE 3B. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
CLK0, nCLK0
CLK1, nCLK1
0
1
Selected
De-selected
Selected
De-selected
TABLE 3C. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Q0 thru Q23
LOW
Input to Output Mode
Polarity
OE
1
CLK0, CLK1
nCLK0, nCLK1
0
1
Differential to Single Ended
Differential to Single Ended
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Single Ended to Differential
Non Inverting
Non Inverting
Non Inverting
Non Inverting
Inverting
1
1
0
HIGH
1
0
Biased; NOTE 1
LOW
1
1
Biased; NOTE 1
HIGH
1
Biased; NOTE 1
Biased; NOTE 1
0
1
HIGH
1
LOW
Inverting
NOTE 1: Please refer to the Application Information section on page 11, Figure 8, which discusses wiring the differential
input to accept single ended levels.
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ICS8344-01
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
Supply Voltage, VDDx
4.6V
Inputs, VI
-0.5V to VDD + 0.5V
-0.5V to VDDO + 0.5V
Outputs, VO
Package Thermal Impedance, θJA
Storage Temperature, TSTG
47.9°C/W (0lfpm)
-65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings
are stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in
the DC Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended
periods may affect product reliability.
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
VDDO
IDD
Positive Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
95
V
V
Output Supply Voltage
Quiescent Power Supply Current
mA
TABLE 4B. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK_SEL, CLK_EN,
OE
CLK_SEL, CLK_EN,
OE
VIH
VIL
Input High Voltage
2
3.8
0.8
V
V
Input Low Voltage
Input High Current
-0.3
CLK_EN, OE
CLK_SEL
VDD = VIN = 3.465V
5
µA
µA
µA
µA
IIH
V
DD = VIN = 3.465V
DD = 3.465, VIN = 0V
VDD = 3.465, VIN = 0V
150
CLK_EN, OE
CLK_SEL
V
-150
-5
IIL
Input Low Current
V
DD = VDDO = 3.135V
IOH = -36mA
VOH
VOL
Output High Voltage
Output Low Voltage
2.7
V
V
VDD = VDDO = 3.135V
IOL = 36mA
0.5
TABLE 4C. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum
Typical
Maximum Units
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
VDD = VIN = 3.465V
5
µA
µA
µA
µA
V
VDD = VIN = 3.465V
150
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-150
-5
IIL
Input Low Current
VPP
Peak-toPeak Input Voltage
0.3
0.9
1.3
2
VCMR
Common Mode Input Voltage: NOTE 1, 2
V
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
8344AY-01
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ICS8344-01
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4D. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Positive Supply Voltage
3.135
2.375
3.3
2.5
3.465
2.625
95
V
V
Output Supply Voltage
Quiescent Power Supply Current
mA
TABLE 4E. LVCMOS DC CHARACTERISTICS, VDDI = VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK_SEL, CLK_EN,
OE
CLK_SEL, CLK_EN,
OE
VIH
VIL
Input High Voltage
2
3.8
0.8
V
V
Input Low Voltage
Input High Current
-0.3
CLK_EN, OE
CLK_SEL
VDD = VIN = 3.465V
5
µA
µA
µA
µA
IIH
V
DD = VIN = 3.465V
150
CLK_EN, OE
CLK_SEL
VDD = 3.465, VIN = 0V
-150
-5
IIL
Input Low Current
VDD = 3.465, VIN = 0V
VDD = 3.135V
VOH
Output High Voltage
V
DDO = 2.375V
1.9
V
V
IOH = -27mA
VDD = 3.135V
VOL
Output Low Voltage
VDDO = 2.375V
0.4
I
OL = 27mA
TABLE 4F. DIFFERENTIAL DC CHARACTERISTICS, VDD = 3.3V±5%, VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
VDD = VIN = 3.465V
VDD = VIN = 3.465V
Minimum Typical Maximum Units
nCLK0, nCLK1
CLK0, CLK1
5
µA
µA
150
VDD = 3.465V,
VIN = 0V
VDD = 3.465V,
VIN = 0V
nCLK0, nCLK1
CLK0, CLK1
-150
-5
µA
µA
IIL
Input Low Current
VPP
Peak-to-Peak Input Voltage
0.3
0.9
1.3
2
V
V
VCMR
Common Mode Input Voltage; NOTE 1, 2
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4G. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
VDDO
IDD
Positive Supply Voltage
2.375
2.375
2.5
2.5
2.625
2.625
95
V
V
Output Supply Voltage
Quiescent Power Supply Current
mA
TABLE 4H. LVCMOS DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK_SEL, CLK_EN,
OE
CLK_SEL, CLK_EN,
OE
VIH
VIL
Input High Voltage
2
2.9
0.8
V
V
Input Low Voltage
Input High Current
-0.3
CLK_EN, OE
CLK_SEL
VDD = VIN = 2.625V
5
µA
µA
µA
µA
IIH
VDD = VIN = 2.625V
150
CLK_EN, OE
CLK_SEL
VDD = 2.625, VIN = 0V
VDD = 2.625, VIN =0V
VDD = VDDO = 2.375V
-150
-5
IIL
Input Low Current
VOH
VOL
Output High Voltage
Output Low Voltage
1.9
V
V
I
OH = -27mA
VDD = VDDO = 2.375V
IOL = 27mA
0.4
TABLE 4I. DIFFERENTIAL DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = 0°C TO 70°C
Symbol Parameter
IIH Input High Current
Test Conditions
Minimum Typical Maximum Units
nCLK0, nCLK1
CLK0, CLK1
nCLK0, nCLK1
CLK0, CLK1
VDD = VIN = 2.625V
5
µA
µA
µA
µA
V
V
DD = VIN = 2.625V
150
V
DD = 2.625V, VIN = 0V
DD = 2.625V, VIN = 0V
-150
-5
IIL
Input Low Current
V
VPP
Peak-to-Peak Input Voltage
0.3
0.9
1.3
2
VCMR
Common Mode Input Voltage; NOTE 1, 2
V
NOTE 1: For single ended applications, the maximum input voltage for CLK0, nCLK0 and CLK1, nCLK1 is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
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LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 5. AC CHARACTERISTICS, VDD = VDDO = 3.3V±5%; VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%;
DD = VDDO = 2.5V ± 5%, TA = 0°C TO 70°C
V
Symbol Parameter
fMAX Maximum Output Frequency
tPD Propagation Delay, NOTE 1
Q0 - Q7
Test Conditions
Minimum
Typical
Maximum Units
250
5
MHz
ns
0MHz ≤ f ≤ 200MHz
2.5
85
ps
Bank Skew;
NOTE 2, 6
Measured on the rising edge of
VDDO/2
tsk(b)
Q8 - Q15
180
100
ps
Q16 - Q23
ps
Measured on the rising edge of
VDDO/2
tsk(o)
Output Skew; NOTE 3, 6
200
900
ps
ps
Measured on the rising edge of
VDDO/2
tsk(pp) Part-to-Part Skew; NOTE 4, 6
tR
tF
Output Rise Time; NOTE 5
Output Fall Time; NOTE 5
30% to 70%
30% to 70%
200
200
800
800
ps
ps
tCYCLE/2
- 0.25
tCYCLE/2
+ 0.25
0MHz ≤ f ≤ 200MHz
tCYCLE/2
2.5
%
odc
Output Duty Cycle
f = 200MHz
f = 10MHz
f = 10MHz
2.25
2.75
5
ns
ns
ns
tEN
Output Enable Time; NOTE 5
Output Disable TIme; NOTE 5
tDIS
4
All parameters measured at 200MHz and VPPtyp unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output crossing point.
NOTE 2: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 3: Defined as skew across banks of outputs at the same supply voltages and with equal load conditions.
NOTE 4: Defined as between outputs at the same supply voltages ane with equal load conditions. Measured at the
output differential cross points.
NOTE 5: These parameters are guaranteed by characterization. Not tested in production.
NOTE 6: This parameter is defined in accordance with JEDEC Standard 65.
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LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
VDDO
VDD
SCOPE
LVCMOS
VDD = +1.65V
VDDO = 1.65V
Qx
GND = -1.65V
FIGURE 1A - 3.3V OUTPUT LOAD TEST CIRCUIT
VDDO
SCOPE
LVCMOS
Qx
VDDO = +1.25V
GND = -1.25V
FIGURE 1B - 2.5V OUTPUT LOAD TEST CIRCUIT
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LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
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VDD
CLK0, CLK 1
VPP
VCMR
Cross Points
nCLK0, nCLK1
GND
FIGURE 2 - DIFFERENTIAL INPUT LEVEL
Qx
Qy
tsk(o)
FIGURE 3 - OUTPUT SKEW
PART 1
Qx
PART 2
Qy
tsk(pp)
FIGURE 4 - PART-TO-PART SKEW
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DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
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70%
70%
VSWING
30%
30%
Clock Inputs
and Outputs
trise
tfall
FIGURE 5 - INPUT AND OUTPUT RISE AND FALL TIME
nCLK0, nCLK1
CLK0, CLK1
Q0 - Q23
tPD
FIGURE 6 - PROPAGATION DELAY
CLK0, CLK1,
Q0 - Q23
nCLK0, nCLK1
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
FIGURE 7 - odc & tPERIOD
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DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
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APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 8 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF ~ VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit should be located as close as possible to the input pin. The ratio of
R1 and R2 might need to be adjusted to position the V_REF in the center of the input voltage swing. For example, if the input clock
swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
0.1uF
R2
1K
FIGURE 8 - SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8344-01.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8344-01 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VDD_MAX * IDD_MAX = 3.465V * 95mA = 329.2mW
Power (outputs)MAX = 32mW/Loaded Output pair
If all outputs are loaded, the total power is 24* 32mW = 768mW
Total Power_MAX (3.465V, with all outputs switching) = 329.2mW + 768mW = 1097.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.1097W * 42.1°C/W = 74.6°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 6. Thermal Resistance qJA for 48-pin LQFP, Forced Convection
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVCMOS output driver circuit and termination are shown in Figure 9.
VDDO
Q1
VOUT
RL
50
Ω
FIGURE 9 - LVCMOS DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
DD
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = (V
Pd_L = (V
/R ) * (V
- V
)
OH_MAX
OH_MAX
L
DD_MAX
/R ) * (V
- V
)
OL_MAX
L
DD_MAX
OL_MAX
•
•
For logic high, V = V
= V
– 1.2V
OUT
OH_MAX
DD_MAX
For logic low, V = V
= V
– 0.4V
OUT
OL_MAX
DD_MAX
Pd_H = (1.2V/50Ω) * (2V - 1.2V) = 19.2mW
Pd_L = (0.4V/50Ω) * (2V - 0.4V) = 12.8mW
Total Power Dissipation per output pair = Pd_H + Pd_L= 32mW
8344AY-01
www.icst.com/products/hiperclocks.html
REV. B AUGUST 6, 2001
13
ICS8344-01
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
200
0
500
50.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards 67.8°C/W
55.9°C/W
Multi-Layer PCB, JEDEC Standard Test Boards 47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8344-01 is: 1503
8344AY-01
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REV. B AUGUST 6, 2001
14
ICS8344-01
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - Y SUFFIX
TABLE 8. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
8344AY-01
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REV. B AUGUST 6, 2001
15
ICS8344-01
LOW SKEW, 1-TO-24
DIFFERENTIAL-TO-LVCMOS FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS8344AY-01
Marking
Package
48 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS8344AY-01
ICS8344AY-01
ICS8344AY-01T
48 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8344AY-01
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REV. B AUGUST 6, 2001
16
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