ICS83840BHLF [ICSI]
DDR SDRAM MUX; DDR SDRAM MUX
| 型号： | ICS83840BHLF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | DDR SDRAM MUX |
| 文件： | 总7页 (文件大小：131K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
GENERAL DESCRIPTION
FEATURES
The ICS83840B is a DDR SDRAM MUX and is
• 40 low skew single-ended DIMM ports
• 4 SSTL-2 compatible enable inputs
• Maximum Switching Speed: 3ns
• Output skew: 120ps (maximum)
• Bank skew: 60ps (maximum)
• ron = 8Ω (typical)
ICS
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS.The de-
vice has 10 Host Lines and each host line can
be passed to 4 Data Ports.The 10 channels are
allocated as follows in the DDR SDRAM appli-
HiPerClockS™
cation: 8 data lines, 1 strobe line and 1 DQm line. The Host/
Data Ports are compatible with single-ended SSTL-2 and the
device operates from a 2.5V supply.
• Full 2.5V supply modes
Guaranteed low output skew makes the ICS83840B ideal • 0°C to 70°C ambient operating temperature
for demanding applications which require well defined per-
formance and repeatability.
• Pin compatible with the CBTV4010
SIMPLIFIED SCHEMATIC
LOGIC DIAGRAM
RON
HP0
Sw
0DP0
1DP0
2DP0
3DP0
Sw
Sw
HPx
nDPx
Sw
400Ω
RON
HP9
Sw
0DP9
1DP9
2DP9
3DP9
Sw
nSn
Sw
Sw
nS0
nS1
nS2
nS3
SW
PIN ASSIGNMENT
1
2
3
4
5
6
7
8
9
10
11
A
B
C
D
E
F
G
H
J
VDD
nS2
nc
nS1
nc
1DP0
0DP0
2DP0
3DP0
0DP1
2DP1
HP1
3DP1 0DP2
VDD
nS0
GND
HP0
1DP1
GND
HP2
1DP2
2DP2
nS3
ICS83840B
GND
3DP9
HP9
3DP8
2DP8
HP8
GND
2DP7
3DP2
0DP3
HP3
64-Ball TFBGA
2DP9
1DP9
0DP9
1DP3
2DP3
3DP3
7mm x 7mm x 1.2mm
package body
GND
0DP4
HP4
H Package
Top View
1DP8
0DP8
3DP7
1DP4
2DP4
0DP5
HP7
0DP7
3DP6
2DP6
HP6
GND
3DP5
HP5
3DP4
1DP5
K
L
1DP7
1DP6
0DP6
2DP5
83840BH
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REV. A JANUARY 30, 2004
1
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
TABLE 1. PIN DESCRIPTIONS
Number
A1, B2
Name
Type
Power
Power
Unused
Port
Description
VDD
Positive supply pins.
Power supply ground.
No connect.
B4, B10, D2, G10, K2, K7
A3, C1
GND
nc
A2, B1, C2, B3
nS1, nS2, nS3, nS0
Select pins.
B6, B9, C10, F2, F10,
J2, J10, K3, K6, K9
HP0, HP1, HP2, HP9, HP3,
HP8, HP4, HP7, HP6, HP5
Port
Host ports.
A5, A6, A7, B5
A9, A10, B7, B8
A11, B11, C11, D10
E10, E11, F11, G11
H10, J11, K10, K11
K8, L9, L10, L11
K5, L5, L6, L7
1DP0, 2DP0, 3DP0, 0DP0
2DP1, 3DP1, 0DP1, 1DP1
0DP2, 1DP2, 2DP2, 3DP2
ODP3, 1DP3, 2DP3, 3DP3
0DP4, 1DP4, 3DP4, 2DP4
3DP5, 2DP5, 1DP5, 0DP5
3DP6, 2DP6, 1DP6, 0DP6
0DP7, 3DP7, 2DP7, 1DP7
3DP8, 2DP8, 1DP8, 0DP8
2DP9, 3DP9, 1DP9, 0DP9
Port
Port
Port
Port
Port
Port
Port
Port
Port
Port
DIMM ports.
DIMM ports.
DIMM ports.
DIMM ports.
DIMM ports.
DIMM ports.
DIMM ports.
DIMM ports.
DIMM ports.
DIMM ports.
K4, L1, L2, L3
G2, H2, J1, K1
E1, E2, F1, G1
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
nSx
VI = 0V or VDD
VIN = 1.5V
5
pF
pF
CON
Channel on Capacitance HPx
14
NOTE: Capacitance values are measured at 10MHz and a bias voltage 3V. Capacitance is not production tested.
TABLE 3. FUNCTION TABLE
Control Input
Function
nSx
L
Host Port = DIMM Port
Host Port = Disconnected
DIMM Port = 400Ω to GND
H
83840BH
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REV. A JANUARY 30, 2004
2
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
-0.5V to +3.3V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.3V to VDD + 0.3 V
I
Ports
DC Input Clamp Current, IIK
PackageThermal Impedance, θ
-50mA
50.04°C/W (0 mfps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 2.5V 0.2V, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
IDD
Positive Supply Voltage
Power Supply Current
2.3
2.5
2.7
50
V
µA
TABLE 4B. DC CHARACTERISTICS, VDD = 2.5V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
VIK
Input High Voltage nSx
1.6
V
V
Input Low Voltage nSx
Input Clamp Voltage
0.9
-1.2
100
100
100
13
VDD = 2.3V; II = -18mA
V
nSx
µA
µA
µA
Ω
V
DD = 2.5V; VI = VDD or GND;
Input Leakage
Current
nS = VDD
IL
Host Port
DIMM Port
nS = GND for IIL(test)
V
DD = 2.5V; VA = 0.8V; VB = 1.0V
5
5
8
8
rON
On Resistance; NOTE 1
VDD = 2.5V; VA = 1.7V; VB = 1.5V
13
Ω
NOTE 1: Calculated from the current measure, between the Host and the DIMM terminals at the indicated voltages on
each side of the switch.
TABLE 5. AC CHARACTERISTICS, VDD = 2.5V 0.2V, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Propagation Delay;
NOTE 1, 4
Output
Enable Time
Output
Disable Time
Output Skew;
NOTE 2, 4
Bank Skew;
NOTE 3, 4
From HPx or xDPx to
xDPx or HPx
tPD
80
1.2
1.2
160
250
ps
ns
ns
ps
ps
From nSx to
HPx or nDPx
From nSx to
HPx or nDPx
tEN
tDIS
tOSK
tBSK
Any Port to any Port
120
60
Any Port to any Port
within the same bank
NOTE 1: Measured from VDD/2 of the input to VDD/2 of the output.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 3: Defined as skew within a bank with equal load conditions.
NOTE 4: Not production tested, guaranteed by characterization.
83840BH
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REV. A JANUARY 30, 2004
3
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
PARAMETER MEASUREMENT INFORMATION
VDD = 1.25V 0.1V
VDD
2
SCOPE
VDD
nDPx
nDPy
LVCMOS
VDD
2
GND
tsk(o)
-1.25V 0.1V
This circuit is used for test purposes only,
not intended for application use.
2.5V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Sn
(Low-level
enabling)
2.5V
0V
VDD
2
1.25V
1.25V
XDP0:XDP9
XDP0:XDP9
VDD
2
tsk(o)
tPZH →
tPHZ
→
←
VOH
VOH - 0.15V
Output nDPx
(See Note)
1.25V
VOL
NOTE: The output is high except when disabled by the Sn control.
BANK SKEW (where X denotes outputs in the same bank)
3-STATE OUTPUT ENABLE/DISABLE TIMES
VDD
2
D or H
VDD
2
H or D
t
PD
PROPAGATION DELAY
83840BH
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REV. A JANUARY 30, 2004
4
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
θJA byVelocity (Millimeter Feet per Second)
0
1
2
Two-Layer PCB, JEDEC Standard Test Boards
50.04°C/W
43.18°C/W
41.17°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83840B is: 320
83840BH
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REV. A JANUARY 30, 2004
5
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
PACKAGE OUTLINE - H SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
FBGA
MINIMUM
NOMINAL
MAXIMUM
SYMBOL
64 Balls, 7x7mm, 11x11 Pattern
A
A1
A2
A3
b
1.0
1.1
0.2
1.2
0.165
0.16
0.235
0.24
0.2
0.675
0.25
0.7
0.725
0.35
0.3
D
7.00 BSC
5.00 BSC
7.00 BSC
5.00 BSC
0.50 BSC
D1
E
E1
e
REFERENCE DOCUMENT:JEDEC PUBLICATION 95
83840BH
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REV. A JANUARY 30, 2004
6
ICS83840B
Integrated
Circuit
Systems, Inc.
DDR SDRAM MUX
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS83840BH
Marking
Package
64-Ball TFBGA
Count
416 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS83840BH
ICS83840BH
ICS3840BLF
ICS3840BLF
ICS83840BHT
64-Ball TFBGA on Tape and Reel
64-Ball, Lead Free, TFBGA
64-Ball, Lead Free, TFBGA on Tape and Reel
ICS83840BHLF
ICS83840BHLFT
416 per tray
1000
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
83840BH
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REV. A JANUARY 30, 2004
7
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