ICS83940DYI [ICSI]
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER; 低偏移， 1 - TO- 18 LVPECL - TO- LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS83940DYI |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER |
| 文件： | 总13页 (文件大小：109K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
GENERAL DESCRIPTION
FEATURES
The ICS83940DI is a low skew, 1-to-18 LVPECL-
• 18 LVCMOS/LVTTLoutputs
to-LVCMOS/LVTTL Fanout Buffer and a member
• Selectable LVCMOS_CLK or LVPECLclock inputs
HiPerClockS™
of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS83940DI has
two selectable clock inputs. The PCLK, nPCLK
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
pair can accept LVPECL, CML, or SSTL input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS/LVTTL outputs are designed to
drive 50Ω series or parallel terminated transmission lines.
• LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
The ICS83940DI is characterized at 3.3V, 2.5V or mixed
3.3V core, 2.5V output operating supply modes. Guaranteed
output and part-to-part skew characteristics make the
ICS83940DI ideal for those clock distribution applications
demanding well defined performance and repeatability.
• Part to part skew: 750ps (maximum)
• 3.3V, 2.5V or mixed 3.3V core, 2.5V output supply modes
• -40°C to 85°C ambient operating temperature
• Pin compatible with the MPC940L
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
32 31 30 29 28 27 26 25
PCLK
0
Q6
24
23
22
21
20
19
18
17
1
2
3
4
5
6
7
8
GND
GND
nPCLK
18
Q7
Q0:Q17
Q8
1
LVCMOS_CLK
LVCMOS_CLK
CLK_SEL
PCLK
VDD
Q9
ICS83940DI
10 11 12 13 14 15 16
32-Lead LQFP
Q10
Q11
GND
nPCLK
VDD
VDDO
9
7mm x 7mm x 1.4mm package body
Y Pacakge
Top View
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REV. A DECEMBER 12, 2002
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ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 12, 17, 25
GND
Power
Power supply ground.
3
LVCMOS_CLK
Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
Clock select input. Selects LVCMOS / LVTTL clock
Input Pulldown input when HIGH. Selects PCLK, nPCLK inputs
when LOW. LVCMOS / LVTTL interface levels.
4
CLK_SEL
5
6
PCLK
Input Pulldown Non-inverting differential LVPECL clock input.
Inverting differential LVPECL clock input.
nPCLK
Input
VDD/2 default when left floating.
7, 21
VDD
Power
Power
Core supply pins.
8, 16, 29
VDDO
Output supply pins.
9, 10, 11, 13, 14, Q17, Q16, Q15, Q14, Q13,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Output
Clock outputs. LVCMOS / LVTTL interface levels.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
6
pF
pF
Power Dissipation Capacitance
(per output)
CPD
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
51
KΩ
18
28
Ω
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
PCLK, nPCLK
Selected
LVCMOS_CLK
De-selected
Selected
0
1
De-selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK_SEL LVCMOS_CLK
PCLK
nPCLK
Q0:Q17
LOW
0
0
—
—
0
1
1
0
Differential to Single Ended
Differential to Single Ended
Non Inverting
Non Inverting
HIGH
Biased;
NOTE 1
Biased;
NOTE 1
0
0
—
—
0
1
LOW
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
HIGH
0
0
1
1
—
—
0
Biased; NOTE 1
0
1
HIGH
LOW
LOW
HIGH
Single Ended to Single Ended
Single Ended to Single Ended
Inverting
Inverting
Biased; NOTE 1
—
—
—
—
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
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REV. A DECEMBER 12, 2002
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ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
3.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
DD
Inputs, V
-0.3V to VDD + 0.3V
-0.3V to VDDO + 0.3V
±20mA
I
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, VO
Input Current, IIN
Storage Temperature, T
-40°C to 125°C
STG
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REV. A DECEMBER 12, 2002
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ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4A. DC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
2.4
VDD
0.8
V
V
Input Low Voltage
VPP
Peak-to-Peak Input Voltage
500
1000
mV
Input Common Mode Voltage;
NOTE 1, 2
VCMR
PCLK, nPCLK
V
DD - 1.4
VDD - 0.6
±200
V
IIN
Input Current
µA
V
VOH
VOL
IDD
Output High Voltage
Output Low Voltage
Core Supply Current
IOH = -20mA
IOL = 20mA
2.4
0.5
25
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V ± 5%, TA = -40° TO 85°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
250
MHz
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
1.6
1.8
1.6
1.8
3.0
ns
tpLH
Propagation Delay
Propagation Delay
3.0
3.3
3.2
ns
ns
ns
tpLH
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
150
150
1.4
1.2
1.7
1.4
850
750
1.1
1.1
55
ps
ps
ns
ns
ns
ns
ps
ps
ns
ns
%
Output Skew;
NOTE 3, 5
Measured on
rising edge @VDDO/2
tsk(o)
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
tsk(pp)
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
Measured on
rising edge @VDDO/2
tR
tF
Output Rise Time
Output Fall Time
0.5 to 2.4V
0.5 to 2.4V
0.3
0.3
45
f < 134MHz
50
50
odc
Output Duty Cycle
134MHz ≤ f ≤ 250MHz
40
60
%
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
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REV. A DECEMBER 12, 2002
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ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40° TO 85°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
2.4
VDD
0.8
V
V
Input Low Voltage
VPP
Peak-to-Peak Input Voltage
300
1000
mV
Input Common Mode Voltage;
NOTE 1, 2
VCMR
PCLK, nPCLK
V
DD - 1.4
VDD - 0.6
±200
V
IIN
Input Current
µA
V
VOH
VOL
IDD
Output High Voltage
Output Low Voltage
Core Supply Current
IOH = -20mA
IOL = 20mA
1.8
0.5
25
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V ± 5%, VDDO = 2.5V ± 5%, TA = -40° TO 85°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
250
MHz
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
1.7
1.7
1.6
1.8
3.2
ns
tpLH
Propagation Delay
Propagation Delay
3.0
3.4
3.3
ns
ns
ns
tpLH
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
150
150
1.5
1.3
1.8
1.5
850
750
1.2
1.2
55
ps
ps
ns
ns
ns
ns
ps
ps
ns
ns
%
Output Skew;
NOTE 3, 5
Measured on
rising edge @VDDO/2
tsk(o)
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
tsk(pp)
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
Measured on
rising edge @VDDO/2
tR
Output Rise Time
Output Fall Time
Output Duty Cycle
0.5 to 1.8V
0.5 to 1.8V
f < 134MHz
0.3
0.3
45
tF
odc
50
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
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ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40° TO 85°
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
2
VDD
0.8
V
V
Input Low Voltage
Peak-to-Peak
Input Voltage
Input Common Mode Voltage;
NOTE 1, 2
VPP
PCLK, nPCLK
PCLK, nPCLK
300
1000
mV
V
VCMR
VDD - 1.4
VDD - 0.6
±200
IIN
Input Current
µA
V
VOH
VOL
IDD
Output High Voltage
Output Low Voltage
Core Supply Current
IOH = -12mA
IOL = 12mA
1.8
0.5
25
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V±5%, TA = -40° TO 85°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
200
MHz
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
1.2
1.5
1.5
2
3.8
ns
Propagation Delay;
tpLH
3.2
3.7
3.6
ns
ns
ns
Propagation Delay;
tpLH
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
200
200
2.6
1.7
2.2
1.7
1.2
1.0
1.2
1.2
55
ps
ps
ns
ns
ns
ns
ns
ns
ns
ns
%
Output Skew;
NOTE 3, 5
Measured on
rising edge @VDDO/2
tsk(o)
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
tsk(pp)
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
Measured on
rising edge @VDDO/2
tR
Output Rise Time
Output Fall Time
Output Duty Cycle
0.5 to 1.8V
0.5 to 1.8V
f < 134MHz
0.3
0.3
45
tF
odc
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
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ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PARAMETER MEASUREMENT INFORMATION
1.65V±5%
1.25V±5%
2.05V±5%
SCOPE
SCOPE
VDD,
VDDO
VDD
VDDO
LVCMOS
Qx
Qx
LVCMOS
GND
GND
-1.65V±5%
-1.25V±5%
3.3V/2.5V OUTPUT LOAD AC TEST CIRCUIT
3.3V OUTPUT LOAD AC TEST CIRCUIT
1.25V±5%
VDD
SCOPE
VDD,
VDDO
nPCLK
VPP
VCMR
Cross Points
Qx
LVCMOS
GND
PCLK
GND
-1.25V±5%
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
VDDO
VDDO
2
Qx
2
Qx
PART 2
VDDO
VDDO
2
Qy
2
Qy
tsk(o)
tsk(pp)
PART-TO-PART SKEW
OUTPUT SKEW
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ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
VDD
2
LVCMOS_CLK
nPCLK
PCLK
2.4V
2.4V
VDDO
0.5V
0.5V
2
Q0:Q17
Clock Outputs
tR
tF
➤
tPD
➤
PROPAGATION DELAY
3.3V OUTPUT RISE/FALL TIME
1.8V
1.8V
0.5V
0.5V
Clock Outputs
tR
tF
2.5V OUTPUT RISE/FALL TIME
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ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept
single ended levels. The reference voltage V_REF = VDD/2 is
generated by the bias resistors R1, R2 and C1. This bias circuit
should be located as close as possible to the input pin. The ratio
of R1 and R2 might need to be adjusted to position the V_REF in
the center of the input voltage swing. For example, if the input
clock swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V
and R2/R1 = 0.609.
VDD
R1
1K
CLK_IN
+
V_REF
-
C1
R2
1K
0.1uF
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
55.9°C/W
42.1°C/W
50.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83940DI is: 820
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ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
PACKAGE OUTLINE - Y SUFFIX
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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83940DYI
REV. A DECEMBER 12, 2002
ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS83940DYI
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
-40°C to 85°C
-40°C to 85°C
ICS83940DYI
ICS83940DYI
ICS83940DYI-T
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability, or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices
or critical medical instruments.
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REV. A DECEMBER 12, 2002
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ICS83940DI
LOW SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER
Integrated
Circuit
Systems, Incꢀ
REVISION HISTORY SHEET
Rev
Table
Page
Description of Change
Date
T2
2
Pin Characteristics table - changed ROUT 25Ω maximum to 28Ω maximum.
Delete RPULLUP row.
7
3.3V Output Load AC Test Circuit diagram - corrected GND equation to read
-1.65V... from -1.165V...
A
12/12/02
Added LVTTL to title.
Updated format.
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REV. A DECEMBER 12, 2002
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SI9130LG-T1-E3
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9130_11
Pin-Programmable Dual Controller - Portable PCsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9137
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SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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