ICS83940DYLF [ICSI]
LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER; 低偏移， 1 - TO- 18 LVPECL - TO- LVCMOS / LVTTL扇出缓冲器
| 型号： | ICS83940DYLF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-18 LVPECL-TO-LVCMOS / LVTTL FANOUT BUFFER |
| 文件： | 总15页 (文件大小：296K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS83940D
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS83940D is a low skew, 1-to-18 LVPECL-
• 18 LVCMOS/LVTTL outputs
ICS
to-LVCMOS/LVTTL Fanout Buffer and a member
• Selectable LVCMOS_CLK or LVPECL clock inputs
HiPerClockS™
of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. The ICS83940D has
two selectable clock inputs. The PCLK, nPCLK
• PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
pair can accept LVPECL, CML, or SSTL input levels. The
LVCMOS_CLK can accept LVCMOS or LVTTL input levels.
The low impedance LVCMOS/LVTTL outputs are designed to
drive 50Ω series or parallel terminated transmission lines.
• LVCMOS_CLK accepts the following input levels:
LVCMOS or LVTTL
• Maximum output frequency: 250MHz
• Output skew: 150ps (maximum)
The ICS83940D is characterized at full 3.3V and 2.5V or mixed
3.3V core, 2.5V output operating supply modes. Guaranteed
output and part-to-part skew characteristics make the
ICS83940D ideal for those clock distribution applications
demanding well defined performance and repeatability.
• Part to part skew: 750ps (maximum)
• Additive phase jitter, RMS: < 0.03ps (typical)
• Full 3.3V and 2.5V or mixed 3.3V core, 2.5V output
supply modes
• 0°C to 70°C ambient operating temperature
• Lead-Free package available
• Pin compatible with the MPC940L
BLOCK DIAGRAM
PIN ASSIGNMENT
CLK_SEL
32 31 30 29 28 27 26 25
PCLK
0
Q6
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
GND
nPCLK
18
Q7
Q0:Q17
1
Q8
LVCMOS_CLK
LVCMOS_CLK
CLK_SEL
PCLK
VDD
Q9
ICS83940D
10 11 12 13 14 15 16
32-Lead LQFP
Q10
Q11
GND
nPCLK
VDD
VDDO
9
7mm x 7mm x 1.4mm package body
Y Pacakge
TopView
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REV. B JUNE 15, 2004
1
ICS83940D
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 2, 12, 17, 25
GND
Power
Power supply ground.
3
LVCMOS_CLK
Input Pulldown Clock input. LVCMOS / LVTTL interface levels.
Clock select input. Selects LVCMOS / LVTTL clock
Input Pulldown input when HIGH. Selects PCLK, nPCLK inputs
when LOW. LVCMOS / LVTTL interface levels.
4
CLK_SEL
5
6
PCLK
Input Pulldown Non-inverting differential LVPECL clock input.
Pullup/ Inverting differential LVPECL clock input.
Input
nPCLK
Pulldown VDD/2 default when left floating.
7, 21
VDD
Power
Power
Core supply pins.
8, 16, 29
VDDO
Output supply pins.
9, 10, 11, 13, 14, Q17, Q16, Q15, Q14, Q13,
15, 18, 19, 20, 22,
23, 24, 26, 27, 28,
30, 31, 32
Q12, Q11, Q10, Q9, Q8,
Q7, Q6, Q5, Q4, Q3,
Q2, Q1, Q0
Output
Clock outputs. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
4
pF
Power Dissipation Capacitance
(per output)
CPD
6
pF
RPULLup
Input Pullup Resistor
51
51
KΩ
KΩ
Ω
RPULLDOWN Input Pulldown Resistor
ROUT Output Impedance
18
28
TABLE 3A. CLOCK SELECT FUNCTION TABLE
Control Input
Clock
CLK_SEL
PCLK, nPCLK
Selected
LVCMOS_CLK
De-selected
Selected
0
1
De-selected
TABLE 3B. CLOCK INPUT FUNCTION TABLE
Inputs
Outputs
Input to Output Mode
Polarity
CLK_SEL LVCMOS_CLK
PCLK
nPCLK
Q0:Q17
LOW
0
0
—
—
0
1
1
0
Differential to Single Ended
Differential to Single Ended
Non Inverting
Non Inverting
HIGH
Biased;
NOTE 1
Biased;
NOTE 1
0
0
—
—
0
1
LOW
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
HIGH
0
0
1
1
—
—
0
Biased; NOTE 1
0
1
HIGH
LOW
LOW
HIGH
Single Ended to Single Ended
Single Ended to Single Ended
Inverting
Inverting
Biased; NOTE 1
—
—
—
—
Single Ended to Single Ended Non Inverting
Single Ended to Single Ended Non Inverting
1
NOTE 1: Please refer to the Application Information section, "Wiring the Differential Input to Accept Single Ended Levels".
83940DY
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REV. B JUNE 15, 2004
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ICS83940D
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
3.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.3V to VDD + 0.3V
-0.3V to VDDO + 0.3V
20mA
I
Outputs, VO
Input Current, IIN
StorageTemperature, T
-40°C to 125°C
STG
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REV. B JUNE 15, 2004
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ICS83940D
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
TABLE 4A. DC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0° TO 70°
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
2.4
VDD
0.8
V
V
Input Low Voltage
VPP
Peak-to-Peak Input Voltage
500
1000
mV
Input Common Mode Voltage;
NOTE 1, 2
VCMR
PCLK, nPCLK
V
DD - 1.4
VDD - 0.6
200
V
IIN
Input Current
µA
V
VOH
VOL
IDD
Output High Voltage
Output Low Voltage
Core Supply Current
IOH = -20mA
IOL = 20mA
2.4
0.5
25
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO = 3.3V 5ꢀ, TA = 0° TO 70°
Minimu-
Symbol Parameter
fMAX Output Frequency
Test Conditions
Typical Maximum Units
m
250
3.0
MHz
ns
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
1.6
1.8
1.6
1.8
tpLH
Propagation Delay
Propagation Delay
3.0
3.3
3.2
ns
ns
ns
tpLH
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
150
150
1.4
ps
ps
ns
ns
ns
ns
ps
ps
Output Skew;
NOTE 3, 5
Measured on
rising edge @VDDO/2
tsk(o)
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
tsk(pp)
1.2
1.7
Part-to-Part Skew;
NOTE 6
1.4
850
750
Part-to-Part Skew;
NOTE 4, 5
Measured on
rising edge @VDDO/2
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 7
tjit
0.03
ps
tR / tF
odc
Output Rise/Fall Time
0.5 to 2.4V
f < 134MHz
134MHz ≤ f ≤ 250MHz
0.3
45
40
1.1
55
60
ns
ꢀ
ꢀ
50
50
Output Duty Cycle
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 7: Driving only one input clock.
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REV. B JUNE 15, 2004
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ICS83940D
Integrated
Circuit
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LOW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
TABLE 4B. DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
PCLK, nPCLK
2.4
VDD
0.8
V
V
Input Low Voltage
VPP
Peak-to-Peak Input Voltage
300
1000
mV
Input Common Mode Voltage;
NOTE 1, 2
VCMR
PCLK, nPCLK
VDD - 1.4
VDD - 0.6
200
V
IIN
Input Current
µA
V
VOH
VOL
IDD
Output High Voltage
Output Low Voltage
Core Supply Current
IOH = -20mA
IOL = 20mA
1.8
0.5
25
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5B. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
250
MHz
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
1.7
1.7
1.6
1.8
3.2
ns
tpLH
Propagation Delay
Propagation Delay
3.0
3.4
3.3
ns
ns
ns
tpLH
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
150
150
1.5
ps
ps
ns
ns
ns
ns
ps
ps
Output Skew;
NOTE 3, 5
Measured on
rising edge @VDDO/2
tsk(o)
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
tsk(pp)
1.3
1.8
Part-to-Part Skew;
NOTE 6
1.5
850
750
Part-to-Part Skew;
NOTE 4, 5
Measured on
rising edge @VDDO/2
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 7
Output Rise/Fall Time
Output Duty Cycle
tjit
0.03
50
ps
tR / tF
odc
0.5 to 1.8V
0.3
45
1.2
55
ns
ꢀ
f < 134MHz
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges, and with equal
load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 7: Driving only one input clock.
83940DY
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REV. B JUNE 15, 2004
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ICS83940D
Integrated
Circuit
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LOW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
TABLE 4C. DC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
LVCMOS_CLK
LVCMOS_CLK
2
VDD
0.8
V
V
Input Low Voltage
Peak-to-Peak
Input Voltage
Input Common Mode Voltage;
NOTE 1, 2
VPP
PCLK, nPCLK
PCLK, nPCLK
300
1000
mV
V
VCMR
V
DD - 1.4
VDD - 0.6
200
IIN
Input Current
µA
V
VOH
VOL
IDD
Output High Voltage
Output Low Voltage
Core Supply Current
IOH = -12mA
IOL = 12mA
1.8
0.5
25
V
mA
NOTE 1: For single ended applications, the maximum input voltage for PCLK, nPCLK is VDD + 0.3V.
NOTE 2: Common mode voltage is defined as VIH.
TABLE 5C. AC CHARACTERISTICS, VDD = VDDO = 2.5V 5ꢀ, TA = 0° TO 70°
Symbol Parameter
fMAX Output Frequency
Test Conditions
Minimum Typical Maximum Units
200
MHz
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
PCLK, nPCLK;
NOTE 1, 5
LVCMOS_CLK;
NOTE 2, 5
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
1.2
1.5
1.5
2
3.8
ns
Propagation Delay;
tpLH
3.2
3.7
3.6
ns
ns
ns
Propagation Delay;
tpLH
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
PCLK, nPCLK
LVCMOS_CLK
200
200
2.6
1.7
2.2
1.7
1.2
1.0
ps
ps
ns
ns
ns
ns
ns
ns
Output Skew;
NOTE 3, 5
Measured on
rising edge @VDDO/2
tsk(o)
f ≤ 150MHz
f ≤ 150MHz
f > 150MHz
f > 150MHz
Part-to-Part Skew;
NOTE 6
tsk(pp)
tsk(pp)
tsk(pp)
Part-to-Part Skew;
NOTE 6
Part-to-Part Skew;
NOTE 4, 5
Measured on
rising edge @VDDO/2
Buffer Additive Phase Jitter, RMS;
refer to Additive Phase Jitter section,
NOTE 7
tjit
0.03
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
0.5 to 1.8V
0.3
45
1.2
55
ns
ꢀ
f < 134MHz
All parameters measured at 200MHz unless noted otherwise.
NOTE 1: Measured from the differential input crossing point to the output VDDO/2.
NOTE 2: Measured from VDD/2 to VDDO/2.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions. Measured at VDDO/2.
NOTE 4: Defined as skew between outputs on different devices operating at the same supply voltages, same temperature,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 5: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 6: Defined as skew between outputs on different devices, across temperature and voltage ranges,
and with equal load conditions. Using the same type of inputs on each device, the outputs are measured at VDDO/2.
NOTE 7 Driving only one input clock.
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REV. B JUNE 15, 2004
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ICS83940D
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LOW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
ADDITIVE PHASE JITTER
the 1Hz band to the power in the fundamental. When the re-
quired offset is specified, the phase noise is called a dBc value,
which simply means dBm at a specified offset from the funda-
mental. By investigating jitter in the frequency domain, we get a
better understanding of its effects on the desired application over
the entire time record of the signal. It is mathematically possible
to calculate an expected bit error rate given a phase noise plot.
The spectral purity in a band at a specific offset from the funda-
mental compared to the power of the fundamental is called the
dBc Phase Noise. This value is normally expressed using a
Phase noise plot and is most often the specified plot in many
applications. Phase noise is defined as the ratio of the noise
power present in a 1Hz band at a specified offset from the fun-
damental frequency to the power value of the fundamental.This
ratio is expressed in decibels (dBm) or a ratio of the power in
0
-10
-20
Input/Output Additive Phase Jitter
at 155.52MHz = 0.03ps (typical)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
1k
10k
100k
1M
10M
100M
OFFSET FROM CARRIER FREQUENCY (HZ)
As with most timing specifications, phase noise measurements vice meets the noise floor of what is shown, but can actually be
have issues.The primary issue relates to the limitations of the lower. The phase noise is dependant on the input source and
equipment. Often the noise floor of the equipment is higher than measurement equipment.
the noise floor of the device. This is illustrated above. The de-
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ICS83940D
Integrated
Circuit
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LOW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
2.05V 5ꢀ
SCOPE
SCOPE
VDD,
VDDO
VDD
VDDO
LVCMOS
Qx
Qx
LVCMOS
GND
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
1.25V 5ꢀ
VDD
SCOPE
VDD,
VDDO
nPCLK
VPP
VCMR
Cross Points
Qx
LVCMOS
GND
PCLK
GND
-1.25V 5ꢀ
2.5V OUTPUT LOAD AC TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART 1
VDDO
VDDO
2
Qx
2
Qx
PART 2
VDDO
VDDO
2
Qy
2
Qy
tsk(o)
tsk(pp)
PART-TO-PART SKEW
OUTPUT SKEW
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LOW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
VDD
2
LVCMOS_CLK
nPCLK
PCLK
2.4V
2.4V
VDDO
0.5V
0.5V
2
Q0:Q17
Clock Outputs
tR
tF
➤
tPD
➤
PROPAGATION DELAY
3.3V OUTPUT RISE/FALL TIME
1.8V
1.8V
0.5V
0.5V
Clock Outputs
tR
tF
2.5V OUTPUT RISE/FALL TIME
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LOW
S
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LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
APPLICATION INFORMATION
WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS
Figure 1 shows how the differential input can be wired to accept of R1 and R2 might need to be adjusted to position theV_REF in
single ended levels. The reference voltage V_REF = VDD/2 is the center of the input voltage swing. For example, if the input
generated by the bias resistors R1, R2 and C1.This bias circuit clock swing is only 2.5V andVDD = 3.3V, V_REF should be 1.25V
should be located as close as possible to the input pin.The ratio and R2/R1 = 0.609.
VDD
R1
1K
Single Ended Clock Input
PCLK
V_REF
nPCLK
C1
0.1u
R2
1K
FIGURE 1. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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LOW
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LVPECL-TO-LVCMOS / LVTTL FANOUT
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LVPECL CLOCK INPUT INTERFACE
The PCLK /nPCLK accepts LVPECL, CML, SSTL and other here are examples only. If the driver is from another vendor,
differential signals. Both VSWING and VOH must meet the VPP use their termination recommendation. Please consult with
and VCMR input requirements. Figures 2A to 2F show interface the vendor of the driver component to confirm the driver ter-
examples for the HiPerClockS PCLK/nPCLK input driven by mination requirements.
the most common driver types.The input interfaces suggested
3.3V
3.3V
3.3V
3.3V
3.3V
R1
50
R2
50
Zo = 50 Ohm
Zo = 50 Ohm
CML
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
R1
100
nPCLK
nPCLK
HiPerClockS
HiPerClockS
PCLK/nPCLK
PCLK/nPCLK
CML Built-In Pullup
FIGURE 2A. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN OPEN COLLECTOR CML DRIVER
FIGURE 2B. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A BUILT-IN PULLUP CML DRIVER
3.3V
3.3V
3.3V
3.3V
3.3V
3.3V
R3
125
R4
125
R3
84
R4
84
C1
C2
Zo = 50 Ohm
Zo = 50 Ohm
3.3V LVPECL
Zo = 50 Ohm
Zo = 50 Ohm
PCLK
PCLK
nPCLK
HiPerClockS
PCLK/nPCLK
nPCLK
HiPerClockS
Input
LVPECL
R5
100 - 200
R6
100 - 200
R1
125
R2
125
R1
84
R2
84
FIGURE 2C. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER
FIGURE 2D. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVPECL DRIVER WITH AC COUPLE
3.3V
2.5V
3.3V
3.3V
3.3V
2.5V
Zo = 50 Ohm
R3
1K
R4
1K
R3
120
R4
120
C1
C2
LVDS
SSTL
Zo = 60 Ohm
Zo = 60 Ohm
PCLK
PCLK
R5
100
nPCLK
nPCLK
Zo = 50 Ohm
HiPerClockS
PCLK/nPCLK
HiPerClockS
PCLK/nPCLK
R1
1K
R2
1K
R1
120
R2
120
FIGURE 2E. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY AN SSTL DRIVER
FIGURE 2F. HIPERCLOCKS PCLK/nPCLK INPUT DRIVEN
BY A 3.3V LVDS DRIVER
83940DY
www.icst.com/products/hiperclocks.html
11
REV. B JUNE 15, 2004
ICS83940D
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS83940D is: 820
83940DY
www.icst.com/products/hiperclocks.html
REV. B JUNE 15, 2004
12
ICS83940D
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
83940DY
www.icst.com/products/hiperclocks.html
13
REV. B JUNE 15, 2004
ICS83940D
Integrated
Circuit
Systems, Inc.
LOW
S
KEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS83940DY
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS83940DY
ICS83940DY
ICS83940DYT
32 Lead LQFP on Tape and Reel
32 Lead "Lead Free" LQFP
32 Lead "Lead Free" LQFP on Tape and Reel
ICS83940DYLF
ICS83940DYLFT
ICS83940DYLF
ICS83940DYLF
250 per tray
1000
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for
use in life support devices or critical medical instruments.
83940DY
www.icst.com/products/hiperclocks.html
REV. B JUNE 15, 2004
14
ICS83940D
Integrated
Circuit
Systems, Inc.
LOW
SKEW, 1-TO-18
LVPECL-TO-LVCMOS / LVTTL FANOUT
BUFFER
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
T5A
4
3.3V AC Characteristics table -
• tsk(pp) Test Conditions, replaced "<" with " ≤ "; corrected Units to "ns" from "ps".
• odc - corrected Test Conditions to read "134MHz ≤ f ≤ 250MHz", from
"f ≤ 250MHz".
A
10/11/02
12/12/02
3.3V/2.5V AC Characteristics table - tsk(pp) Test Conditions,
replaced "<" with " ≤ "; corrected Units to read "ns" from "ps".
T5B
5
6
2
2.5V AC Characteristics table - tsk(pp) Test Conditions,
replaced "<" with " ≤ "; corrected Units to "ns" from "ps".
Pin Characteristics table - changed ROUT 25Ω maximum to 28Ω maximum.
Delete RPULLUP row.
T5C
T2
7
3.3V Output Load AC Test Circuit diagram - corrected GND equation to read
-1.65V... from -1.165V...
A
Added LVTTL to title.
Updated format.
T1
T2
2
2
4
Pin Description Table - added Pullup and Pulldown to Pin 6, nPCLK.
Pin Characteristics Table - added RPULLUP row.
Added tjit row.
T5A
T5B T5C
5
Added tjit row.
B
B
10/9/03
6/15/04
6
7
Added tjit row.
Added Additive Phase Jitter section.
Updated Single Ended Signal Driving Differential Input diagram.
Added LVPECL Clock Interface section.
Added "Lead-Free" bullet to Features section.
Added NOTE 7.
10
11
1
4 - 6
11
14
T5A - T5C
Updated LVPECL Clock Input Interface section.
Ordering Information table - added "Lead-Free" part number.
83940DY
www.icst.com/products/hiperclocks.html
REV. B JUNE 15, 2004
15
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