ICS839893AYIT [ICSI]
LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER; 低偏移， 1到13 LVCMOS / LVTTL缓冲分压器
| 型号： | ICS839893AYIT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | LOW SKEW, 1-TO-13 LVCMOS/LVTTL BUFFER DIVIDER |
| 文件： | 总10页 (文件大小：141K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
Integrated
Circuit
Systems, Inc.
FEATURES
GENERAL DESCRIPTION
• 13 LVCMOS/LVTTL outputs: 3 banks (6, 6, 1 outputs per
bank respectively)
The ICS839893I is a high-performance one to
ICS
HiPerClockS™
thirteen LVCMOS/LVTTL buffer/divider and is
a member of the HiPerClockS™ family of High
Performance Clock Solutions from ICS. The
device has two selectable LVCMOS/LVTTL
• Selectable CLK0 or CLK1 LVCMOS/LVTTL clock inputs
• CLK0, CLK1 supports the following input types:
LVCMOS, LVTTL
clock inputs and it generates 13 new LVCMOS/LVTTL clock
outputs.The first bank of six outputs offers divide-by-1, 2, 4,
8 or 16.The second bank of six outputs can be configured to
the same divide ratio as the first bank, or with an additional
divide-by-two.The first two banks can be placed into a high-
impedance output state with the assertion of a LOW on the
nOE/MR input. One additional output can be configured
to divide-by-4, 6, 8 or 16. This device is functional with full
3.3V or full 2.5V supplies.
• Maximum output frequency: 250MHz
• Output skew: 40ps (maximum), within bank
• Full 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both, Standard and RoHS/Lead-Free compliant
packages
SIMPLIFIED BLOCK DIAGRAM
PIN ASSIGNMENT
nOE/MR
F
FSEL0 FSEL1
FSEL2QA
0
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
÷1
÷2
÷2
÷4
÷2
36 35 34 33 32 31 30 29 28 27 26 25
CLK0
CLK1
0
0
0
1
1
1
1
0
1
GND
QA0
37
38
39
40
41
42
43
24
23
22
21
20
19
18
17
16
15
14
13
GND
QB0
QA0:QA5
QB0:QB5
D Q
D Q
QA1
QB1
÷16
÷8
VDDO_A
GND
QA2
VDDO_B
GND
QB2
ICS839893I
48-Pin LQFP
7mm x 7mm x 1.4mm
body package
REF_SEL
÷4
0
1
QA3
QB3
÷
2
VDDO_A
GND
QA4
44
45
46
VDDO_B
GND
QB4
Y Package
Top View
FSEL0 FSEL1 FSEL2 QC
0
0
0
÷8
QA5
0
0
0
1
1
1
1
0
1
1
0
0
1
1
1
0
1
0
1
0
1
÷8
÷6
47
48
1
QB5
VDDO_A
VDDO_B
QC
÷8
D Q
2 3 4 5 6 7 8 9 10 11 12
÷4
÷16
÷8
÷4
FSEL[0:2]
FSEL3
839893AYI
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REV.A AUGUST 8, 2005
1
ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1, 12, 16, 20, 24, 29,
32, 37, 41, 45
GND
Power
Supply ground.
2
QC
nc
Output
Bank C output. LVCMOS / LVTTL interface levels.
No connect.
3, 4, 9, 10, 11, 33, 35
Unused
Power
Input
5
VDDO_C
CLK0, CLK1
VDD
Output supply pin for Bank C output.
6, 7
Pulldown LVCMOS / LVTTL clock inputs.
8, 25, 36
13, 17, 21
Power
Power
Core supply pins.
VDDO_B
Output supply pins for Bank B outputs.
14, 15,
18, 19,
22, 23
QB5, QB4
QB3, QB2
QB1, QB0
Output
Bank B outputs. LVCMOS / LVTTL interface levels.
Active High Master Reset. Active Low Output Enable.
When logic LOW, the internal dividers and the outputs are
Pulldown enabled. When logic HIGH, the internal dividers are reset and
the outputs are tri-stated (HiZ). LVCMOS / LVTTL interface
levels.
26
nOE/MR
Input
27,
28,
30,
31
FSEL3,
FSEL2,
FSEL1,
FSEL0
Clock frequency selection and configuration of clock divider
Pulldown
Input
Input
modes. LVCMOS / LVTTL interface levels.
Selects the primary reference clock. When LOW, selects CLK0
Pulldown as the primary clock source. When HIGH, selects CLK1 as the
primary clock source. LVCMOS / LVTTL interface levels.
34
REF_SEL
38, 39
42, 43,
46, 47
QA0, QA1,
QA2, QA3,
QA4, QA5
Output
Power
Bank A outputs. LVCMOS / LVTTL interface levels.
40, 44, 48
VDDO_A
Output supply pins for Bank A outputs.
NOTE: Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum Typical
Maximum Units
CIN
Input Capacitance
4
51
9
pF
kΩ
pF
pF
Ω
RPULLDOWN Input Pulldown Resistor
VDD = VDDA = VDDO_x = 3.465V
VDD = VDDA = VDDO_x = 2.625V
Power Dissipation Capacitance
(per output)
CPD
9
ROUT
Ouput Impedance
14
NOTE: VDDO_X denotes VDDO_A, VDDO_B, VDDO
_
C.
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ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
Integrated
Circuit
Systems, Inc.
TABLE 3. CLOCK FREQUENCY FUNCTION TABLE
Inputs
Outputs
fREF Range
(MHz)
QAx
QBx
QC
FSEL0
FSEL1
FSEL2
FSEL3
fQAx (MHz) fQBx (MHz) fQC0 (MHz)
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
fREF ÷ 1
DC - 250
DC - 250
DC - 250
DC - 250
DC - 250
DC - 250
DC - 250
DC - 250
fREF ÷ 1
fREF ÷ 2
fREF ÷ 2
fREF ÷ 4
fREF ÷ 2
fREF ÷ 16
fREF ÷ 8
fREF ÷ 4
fREF ÷ 8
fREF ÷ 8
fREF ÷ 6
fREF ÷ 8
fREF ÷ 4
fREF ÷ 16
fREF ÷ 8
fREF ÷ 4
fREF ÷ 2
fREF ÷ 2
fREF ÷ 4
fREF ÷ 2
fREF ÷ 4
fREF ÷ 4
fREF ÷ 8
fREF ÷ 2
fREF ÷ 4
fREF ÷ 16
fREF ÷ 32
fREF ÷ 8
fREF ÷ 16
fREF ÷ 4
fREF ÷ 8
839893AYI
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REV.A AUGUST 8, 2005
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ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
-0.5V to VDDO_X + 0.5V
47.9°C/W (0 lfpm)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
Core Supply Voltage
3.135
3.3
3.465
3.465
155
V
VDDO_A,
VDDO_B,
VDDO_C
Output Supply Voltage
Power Supply Current
Output Supply Current
3.135
3.3
V
IDD
mA
mA
IDDO_A,
IDDO_B,
IDDO_C
20
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 2.5 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD
Core Supply Voltage
2.375
2.5
2.625
V
VDDO_A,
VDDO_B,
VDDO_C
Output Supply Voltage
2.375
2.5
2.625
V
IDD
Power Supply Current
Output Supply Current
150
20
mA
mA
IDDO_A,
IDDO_B,
IDDO_C
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ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
Integrated
Circuit
Systems, Inc.
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VDD = 3.3V
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
2
VDD + 0.3
0.8
V
V
VDD = 3.3V
-0.3
CLK0, CLK1,
IIH
Input High Current nOE/MR, REF_SEL
FSEL0:FSEL3
CLK0, CLK1,
Input Low Current nOE/MR, REF_SEL
FSEL0:FSEL3
VDD = VIN = 3.465V
200
0.5
µA
µA
IIL
VDD = 3.465V, VIN = 0V
-5
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.6
V
V
Note 1: Outputs terminated with 50Ω to VDDO_x/2. See Parameter Measurement Information,
3.3V Output Load Test Circuit diagram.
TABLE 4D. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
1.7
VDD + 0.3
0.7
V
V
-0.3
CLK0, CLK1,
IIH
Input High Current nOE/MR, REF_SEL
FSEL0:FSEL3
CLK0, CLK1,
Input Low Current nOE/MR, REF_SEL
FSEL0:FSEL3
VDD = VIN = 2.625V
200
0.5
µA
µA
IIL
VDD = 2.625V, VIN = 0V
-5
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
1.8
V
V
Note 1: Outputs terminated with 50Ω to VDDO_x/2. See Parameter Measurement Information,
2.5V Output Load Test Circuit diagram.
839893AYI
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REV.A AUGUST 8, 2005
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ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
Integrated
Circuit
Systems, Inc.
TABLE 5A. AC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
fREF
tPD
Output Frequency
DC
DC
4.5
250
250
6.5
40
MHz
MHz
ns
Input Frequency
Propagation Delay;NOTE 1
within bank
ps
tsk(o)
Output Skew; NOTE 2 bank-to-bank
any output to QC
Excludes QC
20ꢀ to 80ꢀ
115
465
600
10
ps
ps
tR/tF
Output Rise/Fall Time
250
47
ps
t
t
PZL, tPZH Output Enable Time
PLZ, tPHZ Output Disable Time
Output Duty Cycle
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 output crossing point.
ns
10
ns
odc
53
ꢀ
TABLE 5B. AC CHARACTERISTICS, VDD = VDDO_A = VDDO_B = VDDO_C = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
fREF
tPD
Output Frequency
DC
DC
5
250
250
7
MHz
MHz
ns
Input Frequency
Propagation Delay; NOTE 1
within bank
40
ps
Output Skew;
bank-to-bank
NOTE 2
Excludes QC
20ꢀ to 80ꢀ
110
410
600
10
ps
tsk(o)
any output to QC
ps
tR/tF
Output Rise/Fall Time
250
47
ps
t
PZL, tPZH Output Enable Time
PLZ, tPHZ Output Disable Time
Output Duty Cycle
ns
t
10
ns
odc
53
ꢀ
All parameters measured at fMAX unless noted otherwise.
NOTE 1: Measured from VDD/2 of the input to VDDO/2 output crossing point.
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ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
VDD,
VDDO_A,
VDDO_B, VDDO_C
LVCMOS
GND
VDD,
VDDO_A,
VDDO_B, VDDO_C
LVCMOS
Qx
Qx
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V CORE/2.5V OUTPUT LOAD AC TEST CIRCUIT
VDDOX
2
VDDOX
QX0:QX5
Qx
2
VDDOX
2
VDDOX
QX0:QX5
Qy
2
tsk(o)
tsk(b)
OUTPUT SKEW
BANK SKEW (where X denotes outputs in the same bank)
Sn
2.5V
(Low-level
enabling)
1.25V
1.25V
VDDOX
2
0V
QA0:5,
QB0:5, QC
tPW
tPERIOD
VOL
VOH
tPZH
tPHZ
tPW
V
OH - 0.15V
x 100ꢀ
odc =
Output nDPx
(See Note)
1.25V
tPERIOD
VOL
NOTE: The output is high except when disabled by the Sn control.
OUTPUT ENABLE/DISABLE TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
CLK0,
CLK1
2
80ꢀ
80ꢀ
tR
20ꢀ
20ꢀ
VDDOX
Clock
Outputs
QA0:QA5,
QB0:QB5,
2
tF
t
QC
PD
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
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ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CLK INPUT:
OUTPUTS:
LVCMOS OUTPUT:
For applications not requiring the use of the test clock, it can be All unused LVCMOS output can be left floating.We recommend
left floating.Though not required, but for additional protection, a that there is no trace attached.
1kΩ resister can be tied from the CLK input to ground.
CONTROL PINS:
All control pins have internal pull-ups and pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resister can be used.
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 48 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS839893I is: 4615
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REV.A AUGUST 8, 2005
8
ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX FOR 48 LEAD LQFP
TABLE 7. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBC
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
48
--
--
--
1.60
0.15
1.45
0.27
0.20
A1
A2
b
0.05
1.35
0.17
0.09
1.40
0.22
c
--
D
9.00 BASIC
7.00 BASIC
5.50 Ref.
9.00 BASIC
7.00 BASIC
5.50 Ref.
0.50 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.08
Reference Document: JEDEC Publication 95, MS-026
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REV.A AUGUST 8, 2005
9
ICS839893I
LOW SKEW, 1-TO-13
LVCMOS/LVTTL BUFFER DIVIDER
Integrated
Circuit
Systems, Inc.
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS839893AYI
Marking
Package
Shipping Packaging
tray
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS839893AYI
ICS839893AYI
TBD
48 Lead LQFP
ICS839893AYIT
ICS839893AYILF
ICS839893AYILFT
48 Lead LQFP
1000 tape & reel
tray
48 Lead "Lead-Free" LQFP
48 Lead "Lead-Free" LQFP
TBD
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
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REV.A AUGUST 8, 2005
10
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