ICS840001AGIT [ICSI]
FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER; FEMTOCLOCKS⑩ CRYSTAL -TO LVCMOS / LVTTL频率合成器
| 型号： | ICS840001AGIT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS⑩ CRYSTAL-TO LVCMOS/LVTTL FREQUENCY SYNTHESIZER |
| 文件： | 总11页 (文件大小：173K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS840001I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
The ICS840001I is a Fibre Channel Clock • 1 LVCMOS/LVTTL output, 7Ω typical output impedence
ICS
Generator and a member of the HiPerClocksTM
• Crystal oscillator interface designed for 26.5625MHz,
family of high performance devices from ICS.The
18pF parallel resonant crystal
HiPerClockS™
ICS840001I uses a 26.5625MHz crystal to
synthesize either 106.25MHz or 212.5MHz, using
• Selectable 106.25MHz or 212.5MHz output frequency
• VCO range: 560MHz to 680MHz
the FREQ_SEL pin.The ICS840001I has excellent phase jitter
performance, over the 637kHz – 5MHz integration range. The
ICS840001I is packaged in a small 8-pin TSSOP, making it
ideal for use in systems with limited board space.
• RMS phase jitter @ 106.25MHz, using a 26.5625MHz crystal
(637kHz - 5MHz): 0.70ps (typical)
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
FUNCTION TABLE
Input
Output Frequencies
FREQ_SEL
0
1
106.25MHz (Default)
212.5MHz
Crystal: 26.5625MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
(Pullup)
OE
VDDA
OE
VDD
1
2
3
4
8
7
6
5
(Pulldown)
FREQ_SEL
Q
XTAL_OUT
XTAL_IN
GND
FREQ_SEL
1
0
÷3
÷6
VCO
XTAL_IN
OSC
XTAL_OUT
ICS840001I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
Phase
Detector
Q
637.5MHz w/
26.5625MHz Ref.
G Package
TopView
M = ÷24 (fixed)
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
840001AGI
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REV. A JUNE 20, 2005
1
PRELIMINARY
ICS840001I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Description
1
VDDA
Power
Input
Analog supply pin.
Output enable pin. When HIGH, Q output is enabled.
When LOW, forces Q to HiZ state. LVCMOS/LVTTL interface levels.
Crystal oscillator interface. XTAL_IN is the input.
XTAL_OUT is the output.
2
OE
Pullup
XTAL_OUT,
XTAL_IN
3, 4
Input
5
6
FREQ_SEL
GND
Input
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Power supply ground.
Power
Single-ended clock output. LVCMOS/LVTTL interface levels.
7Ω typical output impedance.
Core supply pin.
7
8
Q
Output
Power
VDD
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical Maximum Units
CIN
Input Capacitance
4
TBD
TBD
51
pF
pF
pF
kΩ
kΩ
Ω
VDD, VDDA = 3.465V
CPD
Power Dissipation Capacitance
VDD, VDDA = 2.625V
RPULLUP
RPULLDOWN
ROUT
Input Pullup Resistor
Input Pulldown Resistor
Output Impedance
51
5
7
12
TABLE 3. CONTROL FUNCTION TABLE
Control Inputs
Output
Q
OE
0
Hi-Z
1
Active
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REV. A JUNE 20, 2005
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PRELIMINARY
ICS840001I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
-0.5V to VDD + 0.5V
101.7°C/W (0 mps)
-65°C to 150°C
I
Outputs, VO
PackageThermal Impedance, θ
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
3.465
3.465
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
75
mA
mA
IDDA
8
TABLE 4B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
2.625
2.625
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
2.375
2.5
V
73
mA
mA
IDDA
8
TABLE 4C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
DD = 3.3V
VDD = 2.5V
DD = 3.3V
V
2
VDD + 0.3
VDD + 0.3
0.8
V
V
VIH
VIL
IIH
Input High Voltage
1.7
-0.3
-0.3
V
V
Input Low Voltage
Input High Current
Input Low Current
VDD = 2.5V
0.7
V
FREQ_SEL
OE
V
DD = VIN = 3.465V or 2.625V
150
µA
µA
µA
µA
V
VDD = VIN = 3.465V or 2.625V
DD = 3.465V or 2.625V, VIN = 0V
5
FREQ_SEL
OE
V
-5
-150
2.6
IIL
VDD = 3.465V or 2.625V, VIN = 0V
DD = 3.465V
V
VOH
VOL
Output High Voltage; NOTE 1
VDD = 2.625V
1.8
V
Output Low Voltage; NOTE 1
VDD = 3.465V or 2.625V
0.5
V
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section,
"Output Load Test Circuit" diagrams.
840001AGI
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REV. A JUNE 20, 2005
3
PRELIMINARY
ICS840001I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
26.5625
Mode of Oscillation
Frequency
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
TABLE 6A. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
FREQ_SEL = 1
FREQ_SEL = 0
Minimum Typical Maximum Units
186.66
93.33
212.5
226.66
113.33
MHz
MHz
fOUT
Output Frequency
106.25
fOUT = 106.25MHz,
(637kHz to 5MHz)
fOUT = 212.5MHz,
(2.55MHz to 20MHz)
0.70
0.50
ps
ps
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
400
50
ps
ꢀ
All parameters are characterized @ 212.5MHz and 106.25MHz.
NOTE 1: Please refer to the Phase Noise Plots following this section.
TABLE 6B. AC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
FREQ_SEL = 1
FREQ_SEL = 0
Minimum Typical Maximum Units
186.66
93.33
212.5
226.66
113.33
MHz
MHz
fOUT
Output Frequency
106.25
fOUT = 106.25MHz,
(637kHz to 5MHz)
fOUT = 212.5MHz,
(2.55MHz to 20MHz)
0.70
0.50
ps
ps
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
450
50
ps
ꢀ
All parameters are characterized @ 212.5MHz and 106.25MHz.
NOTE 1: Please refer to the Phase Noise Plots following this section.
840001AGI
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REV. A JUNE 20, 2005
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PRELIMINARY
ICS840001I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
TYPICAL PHASE NOISE AT 106.25MHZ
0
-10
-20
-30
-40
Fibre Channel Filter
106.25MHz
RMS Phase Jitter (Random)
637kHz to 5MHz = 0.70ps (typical)
-50
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
Phase Noise Result by adding
Fibre Channel Filter to raw data
-190
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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REV. A JUNE 20, 2005
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PRELIMINARY
ICS840001I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
1.65V 5ꢀ
1.25V 5ꢀ
SCOPE
SCOPE
VDD
VDDA
,
VDD,
VDDA
Qx
Qx
LVCMOS
GND
LVCMOS
GND
-1.65V 5ꢀ
-1.25V 5ꢀ
3.3V OUTPUT LOAD AC TEST CIRCUIT
2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
80ꢀ
tF
80ꢀ
Phase Noise Mask
20ꢀ
20ꢀ
Clock
Outputs
tR
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OUTPUT RISE/FALL TIME
RMS PHASE JITTER
VDD
2
Q
tPW
tPERIOD
tPW
x 100ꢀ
odc =
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
840001AGI
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REV. A JUNE 20, 2005
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PRELIMINARY
ICS840001I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins are
vulnerable to random noise.The ICS840001I provides separate
power supplies to isolate any high switching noise from the out-
puts to the internal PLL.VDD andVDDA should be individually con-
nected to the power supply plane through vias, and bypass ca-
pacitors should be used for each pin. To achieve optimum
jitter performance, power supply isolation is required. Figure 1
illustrates how a 10Ω resistor along with a 10μF and a .01μF
bypass capacitor should be connected to each VDDA pin.
3.3V or 2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS840001I has been characterized with 18pF parallel allel resonant crystal and were chosen to minimize the ppm er-
ror.The optimum C1 and C2 values can be slightly adjusted for
different board layouts.
resonant crystals. The capacitor values, C1 and C2, shown in
Figure 2 below were determined using a 26.5625MHz, 18pF par-
XTAL_OUT
XTAL_IN
C1
33p
X1
18pF Parallel Crystal
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
840001AGI
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REV. A JUNE 20, 2005
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PRELIMINARY
ICS840001I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
LAYOUT GUIDELINE
different board layout, the C1 and C2 may be slightly adjusted
for optimizing frequency accuracy.The output frequency can be
set at either 106.25MHz or 212.5MHz. Leaving the R1 un-in-
stalled (or install 1k Ω pull-down) will set the output frequency at
106.25MHz. Installing the R1 pull up will set the output frequency
at 212.5MHz.
Figure 3A shows a schematic example of the ICS840001I. An
example of LVCMOS termination is shown in this schematic.
Additional LVCMOS termination approaches are shown in the
LVCMOS Termination Application Note. In this example, an 18
pF parallel resonant 26.5625MHz crystal is used.The C1=27pF
and C2=33pF are recommended for frequency accuracy. For
VDD
VDDA
VDD
R2
10
C3
10uF
C4
0.1u
R1
U2
1K
R3
43
VDD
Q
1
8
7
6
5
Zo = 50 Ohm
VDDA
OE
XTAL_OUT
XTAL_IN
VDD
Q
GND
OE
2
3
4
FRE_SEL
FREQ_SEL
C2
33pF
X1
C5
0.1u
LVCMOS
840001I
C1
27pF
VDD=3.3V
FIGURE 3A. ICS840001I SCHEMATIC EXAMPLE
PC BOARD LAYOUT EXAMPLE
Figure 3B shows an example of P.C. board layout. The crystal
X1 footprint in this example allows either surface mount (HC49S)
or through hole (HC49) package. C3 is 0805. C1 and C2 are
0402. Other resistors and capacitors are 0603. This layout as-
sumes that the board has clean analog power and ground planes.
FIGURE 3B. ICS840001I PC BOARD LAYOUT EXAMPLE
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840001AGI
REV. A JUNE 20, 2005
8
PRELIMINARY
ICS840001I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters Per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS840001I is: 1521
840001AGI
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REV. A JUNE 20, 2005
9
PRELIMINARY
ICS840001I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
840001AGI
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REV. A JUNE 20, 2005
10
PRELIMINARY
ICS840001I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO-
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS840001AGI
Marking
001AI
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
8 lead TSSOP
8 lead TSSOP
ICS840001AGIT
001AI
2500 tape & reel
The aforementioned trademarks, HiPerClockS™ and FemtoClocks™ are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
840001AGI
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REV. A JUNE 20, 2005
11
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