ICS840022AG [ICSI]

FEMTOCLOCKS⑩CRYSTAL-TO LVCMOS/LVTTL CLOCK GENERATOR; FEMTOCLOCKS⑩CRYSTAL -TO LVCMOS / LVTTL时钟发生器
ICS840022AG
型号: ICS840022AG
厂家: INTEGRATED CIRCUIT SOLUTION INC    INTEGRATED CIRCUIT SOLUTION INC
描述:

FEMTOCLOCKS⑩CRYSTAL-TO LVCMOS/LVTTL CLOCK GENERATOR
FEMTOCLOCKS⑩CRYSTAL -TO LVCMOS / LVTTL时钟发生器

时钟发生器
文件: 总10页 (文件大小:204K)
中文:  中文翻译
下载:  下载PDF数据表文档文件
PRELIMINARY  
ICS840022  
Integrated  
Circuit  
Systems, Inc.  
FEMTO  
C
LOCKS™CRYSTAL  
-
TO  
-
LVCMOS/LVTTL CLOCK  
GENERATOR  
GENERAL DESCRIPTION  
FEATURES  
The ICS840022 is a Gigabit Ethernet Clock 1 LVCMOS/LVTTL output, 7output impedence  
ICS  
Generator and a member of the HiPerClocksTM  
Crystal oscillator interface designed for 25MHz,  
family of high performance devices from ICS.  
18pF parallel resonant crystal  
HiPerClockS™  
The ICS840022 uses a 25MHz crystal to  
synthesize 125MHz or 62.5MHz.The ICS840022  
Output frequencies: 125MHz or 62.5MHz (selectable)  
has excellent phase jitter performance, over the 1.875MHz –  
20MHz integration range. The ICS840022 is packaged in a  
small 8-pin TSSOP, making it ideal for use in systems with  
limited board space.  
RMS phase jitter @ 125MHz, using a 25MHz crystal  
(1.875MHz - 20MHz): 0.55ps (typical)  
RMS phase noise at 125MHz:  
Offset  
Noise Power  
100Hz ..............-106.3 dBc/Hz  
1KHz ..............-126.3 dBc/Hz  
10KHz ..............-131.7 dBc/Hz  
100KHz ..............-130.8 dBc/Hz  
3.3V operating supply  
0°C to 70°C ambient operating temperature  
Industrial temperature information available upon request  
FUNCTION TABLE  
Inputs  
Output Frequencies  
(with a 25MHz crystal)  
FREQ_SEL  
0
1
125MHz  
62.5MHz  
BLOCK DIAGRAM  
PIN ASSIGNMENT  
OE  
VDDA  
OE  
VDD  
1
2
3
4
8
7
6
5
FREQ_SEL  
Q0  
XTAL_OUT  
XTAL_IN  
GND  
FREQ_SEL  
0
1
÷5  
VCO  
XTAL_IN  
OSC  
XTAL_OUT  
ICS840022  
8-Lead TSSOP  
4.40mm x 3.0mm x 0.925mm  
package body  
Phase  
Detector  
Q0  
560MHz-680MHz  
w/25MHz Ref.  
÷10  
G Package  
TopView  
M = ÷25 (fixed)  
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial  
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.  
840022AG  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 11, 2005  
1
PRELIMINARY  
ICS840022  
Integrated  
Circuit  
Systems, Inc.  
FEMTO  
C
LOCKS™CRYSTAL  
-
TO  
-
LVCMOS/LVTTL CLOCK  
GENERATOR  
TABLE 1. PIN DESCRIPTIONS  
Number  
Name  
Type  
Description  
1
VDDA  
Power  
Input  
Analog supply pin.  
Output enable pin. When HIGH, Q0 output is enabled.  
2
OE  
Pullup  
When LOW, forces Q0 to HiZ state. LVCMOS/LVTTL interface levels.  
Crystal oscillator interface. XTAL_IN is the input,  
XTAL_OUT is the output.  
XTAL_OUT,  
XTAL_IN  
3, 4  
Input  
5
6
FREQ_SEL  
GND  
Input  
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.  
Power supply ground.  
Power  
Single-ended clock output. LVCMOS/LVTTL interface levels.  
7output impedence.  
Core supply pin.  
7
8
Q0  
Output  
Power  
VDD  
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.  
TABLE 2. PIN CHARACTERISTICS  
Symbol  
CIN  
Parameter  
Test Conditions  
Minimum  
Typical Maximum Units  
Input Capacitance  
4
TBD  
51  
pF  
pF  
K  
KΩ  
CPD  
Power Dissipation Capacitance  
Input Pullup Resistor  
VDD, VDDA = 3.465V  
RPULLUP  
RPULLDOWN Input Pulldown Resistor  
ROUT Output Impedance  
51  
15  
TABLE 3. CONROL FUNCTION TABLE  
Control Inputs  
Output  
Q0  
OE  
0
Hi-Z  
1
Active  
840022AG  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 11, 2005  
2
PRELIMINARY  
ICS840022  
Integrated  
Circuit  
Systems, Inc.  
FEMTO  
C
LOCKS™CRYSTAL  
-
TO  
-
LVCMOS/LVTTL CLOCK  
GENERATOR  
ABSOLUTE MAXIMUM RATINGS  
SupplyVoltage, V  
4.6V  
NOTE: Stresses beyond those listed under Absolute  
Maximum Ratings may cause permanent damage to the  
device.These ratings are stress specifications only.Functional  
operation of product at these conditions or any conditions be-  
yond those listed in the DC Characteristics or AC Character-  
istics is not implied. Exposure to absolute maximum rating  
conditions for extended periods may affect product reliability.  
DD  
Inputs, V  
-0.5V to VDD + 0.5 V  
-0.5V to VDD + 0.5V  
101.7°C/W (0 mps)  
-65°C to 150°C  
I
Outputs, VO  
PackageThermal Impedance, θ  
JA  
StorageTemperature, T  
STG  
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C  
Symbol Parameter  
Test Conditions  
Minimum  
3.135  
Typical  
3.3  
Maximum Units  
VDD  
VDDA  
IDD  
Core Supply Voltage  
3.465  
3.465  
V
V
Analog Supply Voltage  
Power Supply Current  
Analog Supply Current  
3.135  
3.3  
45  
mA  
IDDA  
8
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C  
Symbol Parameter Test Conditions Minimum Typical Maximum Units  
VIH  
VIL  
Input High Voltage  
2
VDD + 0.3  
V
V
Input Low Voltage  
-0.3  
0.8  
5
OE  
V
DD = VIN = 3.465V  
µA  
µA  
µA  
µA  
V
IIH  
Input High Current  
FREQ_SEL  
OE  
VDD = VIN = 3.465V  
150  
V
DD = 3.465V, VIN = 0V  
DD = 3.465V, VIN = 0V  
-150  
-5  
IIL  
Input Low Current  
FREQ_SEL  
V
VOH  
VOL  
Output High Voltage; NOTE 1  
Output Low Voltage; NOTE 1  
2.6  
0.5  
V
NOTE 1: Outputs terminated with 50to VDD/2. See Parameter Measurement Information Section,  
"3.3V Output Load Test Circuit".  
TABLE 5. CRYSTAL CHARACTERISTICS  
Parameter  
Test Conditions  
Minimum  
Typical Maximum Units  
Fundamental  
25  
Mode of Oscillation  
Frequency  
MHz  
Equivalent Series Resistance (ESR)  
Shunt Capacitance  
50  
7
pF  
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C  
Symbol Parameter  
Test Conditions  
Minimum Typical Maximum Units  
125  
MHz  
MHz  
fOUT  
Output Frequency  
62.5  
125MHz, (Intergration Range:  
1.875MHz - 20MHz)  
62.5MHz, (Intergration Range:  
1.875MHz - 20MHz)  
0.55  
0.50  
ps  
ps  
tjit(Ø)  
RMS Phase Jitter; NOTE 1  
tR / tF  
odc  
Output Rise/Fall Time  
Output Duty Cycle  
20ꢀ to 80ꢀ  
350  
50  
ps  
NOTE 1: Please refer to the Phase Noise Plot.  
840022AG  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 11, 2005  
3
PRELIMINARY  
ICS840022  
Integrated  
Circuit  
Systems, Inc.  
FEMTO  
C
LOCKS™CRYSTAL  
-
TO  
-
LVCMOS/LVTTL CLOCK  
GENERATOR  
TYPICAL PHASE NOISE AT 62.5MHZ (3.3V)  
0
-10  
-20  
Gb Ethernet Filter  
-30  
-40  
62.5MHz  
RMS Phase Jitter (Random)  
1.875MHz to 20MHz = 0.55ps (typical)  
-50  
-60  
-70  
-80  
-90  
-100  
-110  
-120  
-130  
-140  
Raw Phase Noise Data  
-150  
-160  
-170  
-180  
Phase Noise Result by adding  
Gb Ethernet Filter to raw data  
-190  
100  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET FREQUENCY (HZ)  
TYPICAL PHASE NOISE AT 125MHZ (3.3V)  
0
-10  
-20  
-30  
-40  
-50  
Gb Ethernet Filter  
125MHz  
RMS Phase Jitter (Random)  
1.875MHz to 20MHz = 0.50ps (typical)  
-60  
-70  
-80  
-90  
-100  
-110  
-120  
-130  
-140  
Raw Phase Noise Data  
-150  
-160  
-170  
Phase Noise Result by adding  
Gb Ethernet Filter to raw data  
-180  
-190  
100  
1k  
10k  
100k  
1M  
10M  
100M  
OFFSET FREQUENCY (HZ)  
840022AG  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 11, 2005  
4
PRELIMINARY  
ICS840022  
Integrated  
Circuit  
Systems, Inc.  
FEMTO  
C
LOCKS™CRYSTAL  
-
TO  
-
LVCMOS/LVTTL CLOCK  
GENERATOR  
PARAMETER MEASUREMENT INFORMATION  
1.65V 5ꢀ  
Phase Noise Plot  
SCOPE  
VDD  
Qx  
Phase Noise Mask  
LVCMOS  
GND  
Offset Frequency  
f1  
f2  
-1.65V 5ꢀ  
RMS Jitter = Area Under the Masked Phase Noise Plot  
3.3V OUTPUT LOAD AC TEST CIRCUIT  
RMS PHASE JITTER  
VDD  
80ꢀ  
tF  
80ꢀ  
tR  
2
Q0  
Pulse Width  
tPERIOD  
20ꢀ  
20ꢀ  
Clock  
Outputs  
tPW  
odc =  
tPERIOD  
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD  
OUTPUT RISE/FALL TIME  
840022AG  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 11, 2005  
5
PRELIMINARY  
ICS840022  
Integrated  
Circuit  
Systems, Inc.  
FEMTO  
CLOCKS™CRYSTAL- -  
TO  
LVCMOS/LVTTL CLOCK  
GENERATOR  
APPLICATION INFORMATION  
POWER SUPPLY FILTERING TECHNIQUES  
As in any high speed analog circuitry, the power supply pins are  
vulnerable to random noise.The ICS840022 provides separate  
power supplies to isolate any high switching noise from the out-  
puts to the internal PLL.VDD, andVDDA should be individually con-  
nected to the power supply plane through vias, and bypass ca-  
pacitors should be used for each pin. To achieve optimum  
jitter performance, power supply isolation is required. Figure 1  
illustrates how a 10resistor along with a 10µF and a .01µF  
bypass capacitor should be connected to each VDDA pin.  
3.3V  
VDD  
.01µF  
.01µF  
10Ω  
VDDA  
10µF  
FIGURE 1. POWER SUPPLY FILTERING  
CRYSTAL INPUT INTERFACE  
The ICS840022 has been characterized with 18pF parallel resonant crystal and were chosen to minimize the ppm error.  
resonant crystals. The capacitor values, C1 and C2, shown in The optimum C1 and C2 values can be slightly adjusted for  
Figure 2 below were determined using a 25MHz, 18pF parallel different board layouts.  
XTAL_OUT  
C1  
33p  
X1  
18pF Parallel Crystal  
XTAL_IN  
C2  
22p  
Figure 2. CRYSTAL INPUt INTERFACE  
840022AG  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 11, 2005  
6
PRELIMINARY  
ICS840022  
Integrated  
Circuit  
Systems, Inc.  
FEMTO  
C
LOCKS™CRYSTAL  
-
TO  
-
LVCMOS/LVTTL CLOCK  
GENERATOR  
A
PPLICATION  
S
CHEMATIC  
Figure 3A shows a schematic example of the ICS840022. An output frequency.The C1 = 22pF and C2pF = 33pF are recom-  
example of LVCMOS termination is shown in this schematic. mended for frequency accuracy. For different board layout, the  
C1 and C2 values may be slightly adjusted for optimizing fre-  
Additional LVCMOS termination approaches are shown in the  
LVCMOSTermination Application Note.In this example, an 18pF quency accuracy.  
parallel resonant 25MHz crystal is used for generating 125MHz  
VDD  
VDDA  
C3  
VDD  
R2  
10  
10uF  
C4  
0.1u  
R1  
U1  
1K  
R3  
33  
VDD  
Q
1
8
7
6
5
Zo = 50 Ohm  
VDDA  
OE  
XTAL_OUT  
XTAL_IN  
VDD  
Q0  
GND  
OE  
2
3
4
FRE_SEL  
FREQ_SEL  
C2  
33pF  
X1  
C5  
0.1u  
LVCMOS  
ICS840022  
C1  
22pF  
VDD=3.3V  
F
IGURE 3A. ICS840022 SCHEMATIC  
E
XAMPLE  
PC BOARD  
L
AYOUT  
E
XAMPLE  
Figure 3B shows an example of ICS840022 P.C. board layout.  
The crystal X1 footprint shown in this example allows installa-  
tion of either surface mount HC49S or through-hole HC49 pack-  
age.The footprints of other components in this example are listed  
in the Table 7. There should be at least one decoupling capacitor  
per power pin.The decoupling capacitors should be located as  
close as possible to the power pins. The layout assumes that  
the board has clean analog power ground plane.  
T
ABLE 7. FOOTPRINT  
T
ABLE  
Reference  
C1, C2  
Size  
0402  
0805  
0603  
0603  
C3  
C4, C5  
R1, R2, R3  
NOTE: Table 7, lists component  
sizes shown in this layout example.  
F
IGURE 3B. ICS840022 PC BOARD  
L
AYOUT  
E
XAMPLE  
840022AG  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 11, 2005  
7
PRELIMINARY  
ICS840022  
Integrated  
Circuit  
Systems, Inc.  
FEMTO  
C
LOCKS™CRYSTAL  
-
TO  
-
LVCMOS/LVTTL CLOCK  
GENERATOR  
RELIABILITY INFORMATION  
TABLE 8. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP  
θJA byVelocity (Meters per Second)  
0
1
2.5  
89.8°C/W  
Multi-Layer PCB, JEDEC Standard Test Boards  
101.7°C/W  
90.5°C/W  
TRANSISTOR COUNT  
The transistor count for ICS840022 is: 1984  
840022AG  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 11, 2005  
8
PRELIMINARY  
ICS840022  
Integrated  
Circuit  
Systems, Inc.  
FEMTO  
C
LOCKS™CRYSTAL  
-
TO  
-
LVCMOS/LVTTL CLOCK  
GENERATOR  
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP  
TABLE 9. PACKAGE DIMENSIONS  
Millimeters  
SYMBOL  
Minimum  
Maximum  
N
A
8
--  
1.20  
0.15  
1.05  
0.30  
0.20  
3.10  
A1  
A2  
b
0.05  
0.80  
0.19  
0.09  
2.90  
c
D
E
6.40 BASIC  
0.65 BASIC  
E1  
e
4.30  
4.50  
L
0.45  
0°  
0.75  
8°  
α
aaa  
--  
0.10  
Reference Document: JEDEC Publication 95, MO-153  
840022AG  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 11, 2005  
9
PRELIMINARY  
ICS840022  
Integrated  
Circuit  
Systems, Inc.  
FEMTO  
C
LOCKS™CRYSTAL  
-
TO  
-
LVCMOS/LVTTL CLOCK  
GENERATOR  
TABLE 10. ORDERING INFORMATION  
Part/Order Number  
ICS840022AG  
Marking  
0022A  
Package  
Count  
tube  
Temperature  
0°C to 70°C  
0°C to 70°C  
8 lead TSSOP  
8 lead TSSOP  
ICS840022AGT  
0022A  
2500 tape & reel  
The aforementioned trademarks, HiPerClockS™ and FEMTOCLOCKS™ are a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.  
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use  
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use  
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are  
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS  
product for use in life support devices or critical medical instruments.  
840022AG  
www.icst.com/products/hiperclocks.html  
REV. A JANUARY 11, 2005  
10  

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