ICS8430-51 [ICSI]
600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER; 600MHZ ，低抖动LVCMOS / LVTTL - TO- 3.3V LVPECL频率合成器
| 型号： | ICS8430-51 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 600MHZ, LOW JITTER LVCMOS/ LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总16页 (文件大小：149K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8430-51 is a general purpose, dual output • Dual differential 3.3V LVPECLoutputs
Crystal-to-3.3V Differential LVPECLHigh Frequency
• Selectable crystal oscillator interface
HiPerClockS™
Synthesizer and a member of the HiPerClockS™
or LVCMOS/LVTTL TEST_CLK
family of High Performance Clock Solutions from
ICS. The ICS8430-51 has a selectable TEST_CLK
• Maximum output frequency: 600MHz
• Crystal input frequency range: 14MHz to 25MHz
• VCO range: 200MHz to 700MHz
or crystal inputs. The VCO operates at a frequency range of
200MHz to 700MHz. With FOUT0 configured to divide the
VCO frequency by 2, output frequency steps as small as
2MHz can be achieved using a 16MHz crystal or reference clock.
FOUT1 provides an additional divide by 16 and 180° phase shift.
Output frequencies up to 600MHz can be programmed using
the serial or parallel interfaces to the configuration logic. The low
jitter and frequency range of the ICS8430-51 make it an ideal
clock generator for most clock tree applications.
• Parallel or serial interface for programming counter
and output dividers
• RMS period jitter: 2.6ps (typical)
• Cycle-to-cycle jitter: 17ps (typical)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_SEL
32 31 30 29 28 27 26 25
TEST_CLK
0
M5
M6
M7
M8
N0
N1
N2
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL1
XTAL1
1
TEST_CLK
XTAL_SEL
VCCA
OSC
XTAL2
÷ 16
ICS8430-51
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
VEE
0
1
9
10 11 12 13 14 15 16
MR
VCO
FOUT0
nFOUT0
FOUT1
÷ N
÷ M
÷ 2
nFOUT1
÷16
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
Top View
M0:M8
N0:N2
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
1
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 16MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 5, NOTE 1.
The ICS8430-51 features a fully integrated PLL and therefore requires no external components for setting the loop band-
width. A parallel-resonant, fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector. With a 16MHz crystal, this provides a 1MHz reference frequency. The VCO of the
PLL operates over a range of 200MHz to 700MHz. The output of the M divider is also applied to the phase detector.
The phase detector and the M divider force the VCO output frequency to be 2M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50% output duty cycle.
The programmable features of the ICS8430-51 support two input modes, programmable M divider and N output divider.
The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel mode,
the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 through N2 is passed directly to the M divider
and N output divider. On the LOW-to-HIGH transition of the nP_LOAD input, the data is latched and the M divider remains
loaded until the next LOW transition on nP_LOAD or until a serial event occurs. As a result, the M and N bits can be
hardwired to set the M divider and N output divider to a specific default state that will automatically occur during power-up.
The TEST output is LOW when operating in the parallel input mode. The relationship between the VCO frequency, the crystal
frequency and the M divider is defined as follows:
fxtal
16
x 2M
fVCO =
The M value and the required values of M0 through M8 are shown in Table 3B, Programmable VCO Frequency Function Table.
Valid M values for which the PLL will achieve lock for a 16MHz reference are defined as 100 ≤ M ≤ 350. The frequency out is
defined as follows:
fVCO fxtal 2M
fout
x
=
=
N
16
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the M divider and N output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide and N output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the S_DATA input is passed directly to the M divider and N output
divider on each rising edge of S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the TEST output as follows:
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
S_Data
Output of M divider
CMOS Fout
S
ERIAL LOADING
S_CLOCK
S_DATA
S_LOAD
T1
t
T0
N2
N1
N0 M8 M7 M6 M5 M4 M3 M2 M1 M0
t
S
H
t
nP_LOAD
S
P
ARALLEL LOADING
M0:M8, N0:N2
nP_LOAD
M, N
t
t
H
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
S
*NOTE: The NULL timing slot must be observed.
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
2
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pulldown
Description
1, 2, 3,
28, 29, 30
31, 32,
M5, M6, M7,
M0, M1, M2,
M3, M4
Input
M divider inputs. Data latched on LOW-to-HIGH transition
of nP_LOAD input. LVCMOS / LVTTL interface levels.
4
5, 6
7
M8
N0, N1
N2
Input
Input
Input
Power
Pullup
Pulldown
Pullup
Determines output divider value as defined in Table 3C
Function Table. LVCMOS / LVTTL interface levels.
8, 16
VEE
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS/ LVTTL interface levels.
9
TEST
VCC
Output
Power
Output
Power
Output
10
Core power supply pin.
FOUT1,
nFOUT1
Differential output for the synthesizer with shifted divide by 16.
3.3V LVPECL interface levels.
11, 12
13
VCCO
Output supply pin.
FOUT0,
nFOUT0
14, 15
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Active High Master Reset. When logic HIGH, the internal dividers
are reset causing the true outputs FOUTx to go low and the inverted
17
MR
Input
Pulldown outputs nFOUTx to go high. When logic LOW, the internal dividers
and the outputs are enabled. Assertion of MR does not affect loaded
M, N, and T values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift regiser
on the rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge
of S_CLOCK. LVCMOS / LVTTL interface levels.
18
19
S_CLOCK
S_DATA
Input
Input
Pulldown
Pulldown
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
20
21
S_LOAD
VCCA
Input
Pulldown
Power
Analog supply pin.
Selects between the crystal oscillator or test clock as the PLL
22
XTAL_SEL
Input
Pullup
reference source. Selects XTAL inputs when HIGH. Selects
TEST_CLK when LOW. LVCMOS / LVTTL interface levels.
23
TEST_CLK
Input
Input
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
24, 25
XTAL1, XTAL2
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into the M divider, and when data present at N2:N0 sets
the N output divider value. LVCMOS / LVTTL interface levels.
26
nP_LOAD
Input
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
KΩ
KΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
3
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. Forces outputs LOW.
Data on M and N inputs passed directly to the M
divider and N output divider. TEST output forced LOW.
L
L
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the
M divider and N output divider.
L
L
L
↑
L
L
↑
X
↑
X
H
H
X
X
X
X
Data
Data
L
L
L
L
H
H
H
X
X
X
X
X
X
↓
L
L
X
↑
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
S_DATA passed directly to M divider as it is clocked.
H
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE (NOTE 1)
256
M8
0
128
M7
0
64
M6
1
32
M5
1
16
M4
0
8
M3
0
4
M2
1
2
M1
0
1
M0
0
VCO Frequency
(MHz)
M Divide
200
202
204
206
•
100
101
102
103
•
0
0
1
1
0
0
1
0
1
0
0
1
1
0
0
1
1
0
0
0
1
1
0
0
1
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
696
698
700
348
349
350
1
0
1
0
1
1
1
0
0
1
0
1
0
1
1
1
0
1
1
0
1
0
1
1
1
1
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of
16MHz.
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
4
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
FOUT0, nFOUT0 Output Frequency
(MHz)
N Divider Value
N2
0
N1
0
N0
0
Minimum
100
50
Maximum
350
2
4
0
0
1
175
0
1
0
8
25
87.5
0
1
1
16
1
12.5
200
100
50
43.75
600
1
0
0
1
0
1
2
350
1
1
0
4
175
1
1
1
8
25
87.5
nFOUT0
FOUT0
nFOUT1
FOUT1
FIGURE 2. FOUTX TIMING DIAGRAM
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
5
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5 V
-0.5V to VCCO + 0.5V
I
Outputs, VO
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
VCCO
IEE
Core Supply Voltage
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
3.135
3.3
V
120
10
mA
mA
ICCA
TABLE 4B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK
2
VCC + 0.3
VCC + 0.3
1.3
V
V
V
V
Input
High Voltage
VCO_SEL, S_LOAD, S_DATA,
S_CLOCK, nP_LOAD, MR,
M0:M8, N0:N2, XTAL_SEL
VIH
2
TEST_CLK
-0.3
-0.3
Input
Low Voltage
VCO_SEL, S_LOAD, S_DATA,
S_CLOCK, nP_LOAD,
M0:M8, N0:N2, XTAL_SEL
M0-M7, N0, N1, MR,
VIL
0.8
S_CLOCK, S_DATA, S_LOAD,
TEST_CLK, nP_LOAD
M8, N2, XTAL_SEL,
VCO_SEL
M0-M7, N0, N1, MR,
VCC = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
VCC = VIN = 3.465V
VCC = 3.465V,
S_CLOCK, S_DATA, S_LOAD,
TEST_CLK, nP_LOAD
-5
V
IN = 0V
VCC = 3.465V,
IN = 0V
Input
Low Current
IIL
M8, N2, XTAL_SEL,
VCO_SEL
-150
2.6
µA
V
Output
High Voltage
Output
VOH
VOL
TEST; NOTE 1
TEST; NOTE 1
V
V
0.5
Low Voltage
NOTE 1: Outputs terminated with 50Ω to VCCO/2.
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
6
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VOH
Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical
Maximum Units
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
Peak-to-Peak Output Voltage Swing
VCC - 1.0
VCC - 1.7
1.0
V
V
V
VOL
VSWING
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V. See "Parameter Information" section,
"3.3V Output Load Test Circuit" figure.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
TEST_CLK; NOTE 1
14
14
25
25
MHz
MHz
MHz
fIN
Input Frequency XTAL1, XTAL2; NOTE 1
S_CLOCK
TBD
NOTE 1: For the input crystal and reference frequency range, the M value must be set for the VCO to operate within the
200MHz to 700MHz range. Using the minimum input frequency of 14MHz, valid values of M are 115 ≤ M ≤ 400.
Using the maximum frequency of 25MHz, valid values of M are 64 ≤ M ≤ 224.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
14
50
25
70
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
FMAX
tjit(cc)
tjit(per)
tsk(o)
tR
Output Frequency
600
MHz
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
%
Cycle-to-Cycle Jitter; NOTE 1, 3
Period Jitter, RMS; NOTE 1
Output Skew; NOTE 2, 3
Output Rise Time
17
2.6
50
200
200
5
700
700
tF
Output Fall Time
M, N to nP_LOAD
tS
Setup Time
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
tH
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
odc
Output Duty Cycle
PLL Lock Time
47
53
1
tLOCK
ms
Parameter Measurement Information section.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
7
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO = 2V
SCOPE
nFOUTx
Qx
FOUTx
LVPECL
nFOUTy
nQx
FOUTy
tsk(o)
VEE = -1.3V ± 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
VOH
nFOUTx
FOUTx
VREF
➤
➤
tcycle n
tcycle n+1
➤
➤
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
CYCLE-TO-CYCLE JITTER
nFOUTx
FOUTx
Pulse Width
tPERIOD
tPW
odc =
tPERIOD
odc & tPERIOD
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
8
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8430-51 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 3 illustrates how
a 10Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10 µF
FIGURE 3. POWER SUPPLY FILTERING
CRYSTAL INPUT AND OSCILLATOR INTERFACE
The ICS8430-51 features an internal oscillator that uses an ppm performance over various parallel resonant crystals.
external quartz crystal as the source of its reference frequency. Figure 4C shows the recommended tuning capacitance for
A 16MHz crystal divided by 16 before being sent to the phase various parallel resonant crystals.
detector provides the reference frequency. The oscillator is a
series resonant, multi-vibrator type design. This design provides
better stability and eliminates the need for large on chip capacitors.
Though a series resonant crystal is preferred, a parallel resonant
crystal can be used. A parallel resonant mode crystal used in a
series resonant circuit will exhibit a frequency of oscillation a few
hundred ppm lower than specified. A few hundred ppm translates
to KHz inaccuracy. In general computing applications this level
of inaccuracy is irrelevant. If better ppm accuracy is required, an
external capacitor can be added to a parallel resonant crystal in
series to pin 24. Figure 4A shows how to interface with a crystal.
ICS8430-51
XTAL2
(Pin 25, LQFP)
XTAL1
(Pin 24, LQFP)
Optional
Figures 4A, 4B, and 4C show various crystal parameters
which are recommended only as guidelines. Figure 4A shows
how to interface a capacitor with a parallel resonant crystal.
Figure 3B shows the capacitor value needed for the optimum
FIGURE 4A. CRYSTAL INTERFACE
FIGURE 4B. Recommended tuning capacitance for various parallel
FIGURE 4C. Recommended tuning capacitance for various
resonant crystals.
parallel resonant crystals.
60
100
80
60
40
20
0
14.318
50
15.000
40
16.667
19.440
30
20.000
20
-20
-40
0
10
20
30
40
50
60
24.000
10
-60
0
-80
14 15 16 17 18 19 20 21 22 23 24 25
-100
Crystal Frequency (MHz)
19.44MHz
16MHz
Series Capacitor, C1 (pF)
15.00MHz
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
9
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- drive 50Ω transmission lines. Matched impedance techniques
tion for LVPECL outputs. The two different layouts mentioned should be used to maximize operating frequency and minimize
are recommended only as guidelines.
signal distortion. Figures 5A and 5B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, terminat-
ing resistors (DC current path to ground) or current sources circuit and clock component process variations.
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
Zo = 50Ω
5
2
5
Zo
Zo
2
FIN
FOUT
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
50Ω
FOUT
FIN
50Ω
➤
Zo = 50Ω
VCC - 2V
RTT
1
3
2
3
Zo
RTT =
Zo
Zo
2
(VOH + VOL / VCC –2) –2
FIGURE 5A. LVPECL OUTPUT TERMINATION
FIGURE 5B. LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS8430-51 layout example used in
this layout guideline is shown in Figure 6A. The ICS8430-51
line. The layout in the actual system will depend on the
selected component types, the density of the components,
recommended PCB board layout for this example is shown the density of the traces, and the stack up of the P.C. board.
in Figure 6B. This layout example is used as a general guide-
X1
R7
VDD
U1
10
C11
1
24
23
22
21
20
19
18
17
0.01u
C16
22u
M5
M6
M7
M8
N0
N1
N2
XTAL1
REF_IN
nXTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
REF_IN
XTAL_SEL
2
3
4
5
6
7
8
S_LOAD
S_DATA
S_CLOCK
MR
GND
Termination A
Termination
B (Not shown
in the layout)
VDD
8430-01
IN+
R1
R3
125
125
Zo = 50 Ohm
IN+
IN-
IN-
TL1
Zo = 50 Ohm
R2
50
R1
50
C14
0.1u
C15
0.1u
TL2
R2
84
R4
84
R3
50
FIGURE 6A. SCHEMATIC OF RECOMMENDED LAYOUT
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
10
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
• The traces with 50Ω transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other.Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
• Keep the clock trace on the same layer. Whenever pos-
sible, avoid any vias on the clock traces. Any via on the
trace can affect the trace characteristic impedance and
hence degrade signal quality.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
• Make sure no other signal trace is routed between the
clock trace pair.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VCCA as possible.
The matching termination resistors R1, R2, R3 and R4 should
be located as close to the receiver input pins as possible. Other
termination schemes can also be used but are not shown in
this example.
CLOCK TRACES AND TERMINATION
The component placements, locations and orientations should be
arranged to achieve the best clock signal quality. Poor clock signal
quality can degrade the system performance or cause system fail-
ure. In the synchronous high-speed digital system, the clock signal
is less tolerable to poor signal quality than other signals. Any ring-
ing on the rising or falling edge or excessive ring back can cause
system failure. The trace shape and the trace delay might be re-
stricted by the available space on the board and the component
location. While routing the traces, the clock signal traces should be
routed first and should be locked prior to routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
X1
GND
VCC
VIA
U1
PIN 1
C11
C16
VCCA
R7
Close to the input
pins of the
receiver
R4
R3
TL1N
C15
C14
TL1
R2
R1
TL1, TL2 are 50 Ohm traces and
equal length
FIGURE 6B. PCB BOARD LAYOUT FOR ICS8430-51
www.icst.com/products/hiperclocks.html
8430AY-51
REV. D FEBRUARY 11, 2003
11
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8430-51.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8430-51 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 120mA = 416mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.465V, with all outputs switching) = 416mW + 60.4mW = 476.4mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 8 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.476W * 42.1°C/W = 90°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8. THERMAL RESISTANCE qJA FOR 32-PIN LQFP, FORCED CONVECTION
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
12
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 7.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CCO_MAX
)
= 1.0V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
/R ] * (V
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω] * 1V = 20.0mW
))
/R ] * (V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
13
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8430-51 is: 4,534
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
14
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/ LVTTL-TO-3.3V LVPECLFREQUENCY SYNTHESIZER
PACKAGE OUTLINE - Y SUFFIX
TABLE 10. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
D
9.00 BASIC
7.00 BASIC
5.60
D1
D2
E
9.00 BASIC
7.00 BASIC
5.60
E1
E2
e
0.80 BASIC
0.60
L
0.45
0.75
q
0°
7°
ccc
0.10
Reference Document: JEDEC Publication 95, MS-026
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
15
PRELIMINARY
ICS8430-51
Integrated
Circuit
Systems, Incꢀ
600MHZ, LOW JITTER
LVCMOS/LVTTL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number
ICS8430AY-51
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS8430AY-51
ICS8430AY-51
ICS8430AY-51T
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8430AY-51
www.icst.com/products/hiperclocks.html
REV. D FEBRUARY 11, 2003
16
相关型号：
ICS8430-71B
700MHZ, LOW JITTER, CRYSTAL INTERFACE / LVCMOS-TO-3.3V LVPECL FREQUENCY SYNTHESIZER
ICSI
©2020 ICPDF网 联系我们和版权申明