ICS84324EMT [ICSI]
CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER; 与扇出缓冲器CRYSTAL - TO- 3.3V LVPECL频率合成器
| 型号： | ICS84324EMT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | CRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER WITH FANOUT BUFFER |
| 文件： | 总14页 (文件大小：176K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER
W
ITH
FANOUT
BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS84324 is a Crystal-to-3.3V LVPECL Fre- • 6 differential 3.3V LVPECLoutputs
,&6
quency Synthesizer with Fanout Buffer and a mem-
• Crystal oscillator interface
HiPerClockS™
ber of the HiPerClockS™ family of High Performance
Clock Solutions from ICS. Output frequency can be
programmed using frequency select pins. The low
phase noise characteristics of the ICS84324 make it an ideal clock
source for Fibre Channel 1 and Gigabit Ethernet applications.
• Output frequency range: 53.125MHz to 125MHz
• Crystal input frequency: 25MHz and 25.5MHz
• RMS phase jitter at 106.25MHz, using a 25.5MHz crystal
(637KHz to 10Mhz): 2.69ps
• Phase noise:
Offset
Noise Power
FUNCTION TABLE
100Hz ................. -96 dBc/Hz
1KHz ................. -115 dBc/Hz
10KHz ................. -125 dBc/Hz
100KHz ................. -127 dBc/Hz
Inputs
XTAL
Output Frequency
F_OUT
MR F_SEL1 F_SEL0
1
0
0
0
0
X
0
0
1
1
X
0
1
0
1
LOW
• 3.3V supply voltage
25.5MHz
25.5MHz
25MHz
53.125MHz
106.25MHz
62.5MHz
• 0°C to 70°C ambient operating temperature
• Industrial termperature information available upon request
25MHz
125MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
1
2
3
4
24
23
22
VCCO
F_SEL0
F_SEL1
MR
XTAL1
XTAL2
VEE
XTAL1
OSC
XTAL2
6
Q0:Q5
21
20
19
18
17
16
15
14
13
0
/
Output
Divider
5
6
7
6
/
nQ0:nQ5
1
PLL
8
9
10
11
12
VCCA
VCC
PLL_SEL
VEE
nQ4
Q5
nQ5
Feedback
Divider
VCCO
ICS84324
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
Top View
F_SEL1
MR
PLL_SEL
F_SEL0
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84324EM
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REV. A SEPTEMBER 18, 2003
1
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER
W
ITH
FANOUT
BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
VCCO
Type
Description
Output
Output
Output
Output
Output
Output
Power
Power
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Differential output pair. LVPECL interface levels.
Output supply pins.
3, 4
5, 6
7, 8
9, 10
11, 12
13, 24
16
VCC
Core supply pin.
14, 18
VEE
PLL_SEL
VCCA
Negative supply pins.
Selects between the PLL and crystal inputs as the input to the dividers.
When HIGH, selects PLL. When LOW, selects XTAL1, XTAL2.
LVCMOS / LVTTL interface levels.
15
Input
Pullup
17
Power
Analog supply pin.
19, 20
XTAL2, XTAL1 Input
Crystal oscillator interface. XTAL1 is the input. XTAL2 is the output.
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs
nQx to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
21
MR
Input Pulldown
22
23
F_SEL1
F_SEL0
Input Pulldown Feedback frequency select pin. LVCMOS / LVTTL interface levels.
Input Pullup Output frequency select pin. LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
K
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
K
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PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER
W
ITH
FANOUT
BUFFER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA 50°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
IEE
Core Supply Voltage
3.465
3.465
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
135
20
mA
mA
ICCA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
PLL_SEL, MR,
F_SEL0, F_SEL1
PLL_SEL, MR,
F_SEL0, F_SEL1
VIH
VIL
Input High Voltage
2
V
CC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
MR, F_SEL1
V
CC = VIN = 3.465V
VCC = VIN = 3.465V
CC = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
IIH
PLL_SEL, F_SEL0
MR, F_SEL1
V
-5
IIL
Input Low Current
PLL_SEL, F_SEL0
VCC = 3.465V, VIN = 0V
-150
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 1.4
VCCO - 2.0
0.6
VCCO - 1.0
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 to VCCO - 2V.
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PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Inc.
C
RYSTAL
-
TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER
W
ITH
FANOUT
BUFFER
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
25
25.5
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
FOUT
tsk(o)
tR
Output Frequency
53.125
125
MHz
ps
Output Skew; NOTE 1, 2
Output Rise Time
Output Fall Time
TBD
20% to 80%
20% to 80%
200
200
650
650
ps
tF
ps
odc
tPW
Output Duty Cycle
Output Pulse Width
PLL Lock Time
50
%
tPERIOD/2 - TBD
tPERIOD/2 + TBD
1
ps
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VCCO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
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ICS84324
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER
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ITH
FANOUT
BUFFER
TYPICAL PHASE NOISE AT 106.25MHZ
USING A 25.5MHZ QUARTZ CRYSTAL
0
-10
-20
-30
Jitter
Process Result
10.000
Source
-40
-50
Start Freq.
Hz
Hz
Stop Freq.
40.000M
106.250M
Freq. carrier
Hz
-60
-70
Mode
Integral
Noise only
sec. rms
2.69p
-80
Execute
Plot
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
10
100
1k
10k
100k
1M
10M
100M
637KHz to 10MHz, 2.69ps
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ICS84324
Integrated
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C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER
W
ITH
FANOUT
BUFFER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA = 2V
SCOPE
Qx
nQx
Qx
LVPECL
nQy
Qy
nQx
tsk(o)
VEE = -1.3V ± 0.165
3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
nQ0:nQ5
80%
tF
80%
Q0:Q5
Pulse Width
20%
20%
tPERIOD
Clock
Outputs
tR
tPW
odc =
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS84324
Integrated
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Systems, Inc.
C
RYSTAL
-
TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER
W
ITH
FANOUT
BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS84324 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 24Ω resistor along with a 10µF and a .01µF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01µF
.01µF
24Ω
VCCA
10 µF
FIGURE 2. POWER SUPPLY FILTERING
T
ERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- drive 50Ω transmission lines. Matched impedance techniques
tion for LVPECL outputs.The two different layouts mentioned should be used to maximize operating frequency and minimize
are recommended only as guidelines.
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
(VOH + VOL / VCC – 2) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER
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BUFFER
CRYSTAL INPUT INTERFACE
A crystal can be characterized for either series or parallel mode
operation. The ICS84324 has a built-in crystal oscillator circuit.
This interface can accept either a series or parallel crystal without
additional components and generate frequencies with accuracy
suitable for most applications. Additional accuracy can be
achieved by adding two small capacitors C1 and C2 as shown in
Figure 4.
19
XTAL2
C1
18pF
25MHz X1
20
XTAL1
C2
22pF
ICS84324
Figure 4. CRYSTAL INPUt INTERFACE
SCHEMATIC EXAMPLE
Figure 5A shows a schematic example of using an ICS84324. In recommended to have one decouple capacitor per power pin.
this example, the input is a 25MHz parallel resonant crystal with Each decoupling capacitor should be located as close as pos-
load capacitor CL=18pF. The frequency fine tuning capacitors sible to the power pin. The low pass filter R7, C11 and C16 for
C1 and C2 is 22pF and 18pF respectively. This example also clean analog supply should also be located as close to the VCCA
shows logic control input handling. The configuration is set at pin as possible.
F_SEL[1:0]=11 therefore the output frequency is 125MHz. It is
VCC
U2
VCC
R4
1K
VCC
Zo = 50
Zo = 50
13
14
15
16
17
18
19
20
21
22
23
24
12
11
10
9
8
7
6
5
4
3
VCCO
VEE
PLL_SEL
VCC
VCCA
VEE
XTAL2
XTAL1
MR
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
-
R7
24
VCCA
22p
+
C11
0.1u
C16
10u
C1
R2
50
R1
50
F_SEL1
F_SEL0
X1
F_SEL1
F_SEL0
VCCO
25MHz,18pF
R5
1K
2
1
C2
R3
50
VCC
18p
ICS84324
RU2
1K
RU3
1K
VCC=3.3V
F_SEL1
F_SEL0
VCC
(U1,13)
(U1,16)
(U1,24)
C6
0.1u
C5
0.1u
C3
0.1u
e.g. F_SEL[1:0]=11
RD2
SP
RD3
SP
SP = Spare, Not Installed
FIGURE 5A. ICS84324 SCHEMATIC EXAMPLE
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ICS84324
Integrated
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C
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-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER
W
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FANOUT
BUFFER
• The differential 50Ω output traces should have the
same length.
The following component footprints are used in this layout
example:
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
All the resistors and capacitors are size 0603.
POWER AND
G
ROUNDING
Place the decoupling capacitors C14 and C15, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
• Keep the clock traces on the same layer. Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
CLOCK
T
RACES AND
T
ERMINATION
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location. While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
C
RYSTAL
The crystal X1 should be located as close as possible to the pins
20 (XTAL1) and 19(XTAL2). The trace length between the X1 and
U1 should be kept to a minimum to avoid unwanted parasitic in-
ductance and capacitance. Other signal traces should not be
routed near the crystal traces.
C6
GND
VCC
C1
C5
Signals
VIA
R7
VCCA
C16
C11
X1
C3
C2
50 Ohm Traces
Pin1
U1 ICS84324
F
IGURE 5B. PCB BOARD LAYOUT FOR ICS84324
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-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER
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ITH
FANOUT
BUFFER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84324.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84324 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 135mA = 468mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 6 * 30.2mW = 181mW
Total Power_MAX (3.465V, with all outputs switching) = 468mW + 181mW = 649mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 43°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.649W * 43°C/W = 98°C. This is well below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6. THERMAL RESISTANCE θJA FOR 24-PIN SOIC, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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-TO-3.3V LVPECL
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 6.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 6. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CCO
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CCO_MAX
)
= 1.0V
OH_MAX
(V
- V
CCO_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
/R ] * (V
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω) * 1V = 20.0mW
))
/R ] * (V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
L
L
[(2V - 1.7V)/50Ω) * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC
θJA by Velocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84324 is: 3500
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PACKAGE OUTLINE - M SUFFIX FOR 24 LEAD SOIC
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
15.20
7.40
2.55
0.51
0.32
15.85
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
Reference Document: JEDEC Publication 95, MS-013, MO-119
84324EM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 18, 2003
13
PRELIMINARY
ICS84324
Integrated
Circuit
Systems, Incꢀ
C
RYSTAL
-TO-3.3V LVPECL
FREQUENCY
SYNTHESIZER
W
ITH
FANOUT
BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
ICS84324EM
Marking
Package
Count
Temperature
0°C to 70°C
0°C to 70°C
ICS84324EM
ICS84324EM
24 Lead SOIC
30 per tube
1000
ICS84324EMT
24 Lead SOIC on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
84324EM
www.icst.com/products/hiperclocks.html
REV. A SEPTEMBER 18, 2003
14
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