ICS843252AG-04 [ICSI]
FEMTOCLOCKS? CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR; FEMTOCLOCKS ？ CRYSTAL - TO- 3.3V LVPECL时钟发生器
| 型号： | ICS843252AG-04 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO-3.3V LVPECL CLOCK GENERATOR |
| 文件： | 总12页 (文件大小：160K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS843252-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
• Two differential 3.3V LVPECL output
The ICS843252-04 is a 10Gb/12Gb Ethernet
ICS
HiPerClockS™
Clock Generator and a member of the
HiPerClocksTM family of high performance
devices from ICS. The ICS843252-04 can
synthesize 10 Gigabit Ethernet and 12 Gigabit
• Crystal oscillator interface designed for
18pF parallel resonant crystals
• Crystal input frequency range: 19.33MHz - 30MHz
• Output frequency range: 145MHz - 187.5MHz
• VCO frequency range: 580MHz - 750MHz
Ethernet with a 25MHz crystal. It can also generate SATA
and 10Gb Fibre Channel reference clock frequencies with
the appropriate choice of crystals. The ICS843252-04 has
excellent phase jitter performance and is packaged in a
small 16-pin TSSOP, making it ideal for use in systems with
limited board space.
• RMS phase jitter at 156.25MHz (1.875MHz - 20MHz):
0.39ps (typical)
• 3.3V operating supply
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard and lead-free compliant
packages
CONFIGURATION TABLE WITH 25MHZ CRYSTAL
Inputs
Output Frequency
Application
Crystal Frequency Feedback VCO Frequency
(MHz)
N Output Divide
(MHz)
Divide
(MHz)
25
30
750
4
4
187.5
12 Gigabit Ethernet
10 Gigabit Ethernet
25
25
625
156.25
CONFIGURATION TABLE WITH SELECTABLE CRYSTALS
Inputs
Output Frequency
(MHz)
Application
Crystal Frequency Feedback VCO Frequency
N Output Divide
(MHz)
Divide
(MHz)
20
30
600
4
4
4
4
4
150
159.375
150
SATA
21.25
24
30
637.5
600
10 Gigabit Fibre Channel
SATA
25
25.5
30
25
637.5
750
159.375
187.5
10 Gigabit Fibre Channel
12 Gigabit Ethernet
25
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
D
1
2
3
4
5
6
7
8
nQ1
Q1
VCCO
OE
16
15
14
13
12
11
10
9
XTAL_IN
XTAL_OUT
VEE
REF_CLK
CLK_SEL
VCC
Q
Pulldown
nPLL_SEL
LE
Pulldown
REF_CLK
nPLL_SEL
VCCO
Q0
1
1
0
DIV. N
÷4
Q0
VCCA
FREQ_SEL
XTAL_IN
VCO
nQ0
nQ0
Phase
Detector
580MHz-750MHz
0
OSC
Q1
nQ1
ICS843252-04
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
XTAL_OUT
CLK_SEL
Pulldown
0 = ÷25 (default)
G Package
Top View
1 = ÷30
Pulldown
FREQ_SEL
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
843252AG-04
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REV.A JANUARY 25, 2006
1
PRELIMINARY
ICS843252-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
nQ1, Q1
VCCO
Type
Description
Output
Power
Differential clock outputs. LVPECL interface levels.
Output supply pins.
3, 6
Output enable. When HIGH, clock outputs follow clock input.
When LOW, Qx outputs are forced low, nQx outputs are forced high.
LVCMOS/LVTTL interface levels.
4
5
OE
Input
Input
Pullup
Selects between the PLL and reference clock as input to the divider.
nPLL_SEL
Pulldown When Low, selects PLL. When High, selects reference clock.
LVCMOS/LVTTL interface levels.
7, 8
9
Q0, nQ0
FREQ_SEL
VCCA
Output
Input
Differential clock outputs. LVPECL interface levels.
Pulldown Frequency select pin. LVCMOS/LVTTL interface levels.
Analog supply pin.
10
Power
11
12
VCC
Power
Input
Core supply pin.
Clock select input. When Low, selects crystal inputs. When High,
Pulldown
CLK_SEL
selects REF_CLK. LVCMOS/LVTTL interface levels.
13
14
REF_CLK
VEE
Input
Pulldown Reference clock input. LVCMOS/LVTTL interface levels.
Negative supply pin.
Power
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
15, 16
Input
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characterristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
kΩ
kΩ
RPULLUP
RPULLDOWN
51
51
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REV.A JANUARY 25, 2006
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PRELIMINARY
ICS843252-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
Package Thermal Impedance, θJA 89°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VCC =VCCA =VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VCC
VCCA
ICC
Core Supply Voltage
3.465
3.465
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
Power Supply Current
3.135
3.3
V
60
mA
mA
mA
ICCA
IEE
11
80
TABLE 3B. LVCMOS/LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
REF_CLK,
CLK_SEL,
FREQ_SEL,
nPLL_SEL
V
CC = VIN = 3.465V
VCC = VIN = 3.465V
CC = 3.465V, VIN = 0V
150
5
µA
µA
µA
µA
IIH
Input High Current
OE
REF_CLK,
CLK_SEL,
FREQ_SEL,
nPLL_SEL
V
-5
IIL
Input Low Current
VCC = 3.465V, VIN = 0V
-150
OE
TABLE 3C. LVPECL DC CHARACTERISTICS, VCC =VCCA = VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCCO - 2V.
843252AG-04
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REV.A JANUARY 25, 2006
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PRELIMINARY
ICS843252-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
19.33
30
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 5. AC CHARACTERISTICS, VCC =VCCA =VCCO = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
145
187.5
MHz
156.25MHz @ Integration Range:
1.875MHz - 20MHz
159.375MHz @ Integration Range:
1.875MHz - 20MHz
187.5MHz @ Integration Range:
1.875MHz - 20MHz
0.39
0.38
0.38
ps
RMS Phase Jitter (Random);
NOTE 1
tjit(Ø)
ps
ps
tsk(o)
tR / tF
odc
Output Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
TBD
400
50
ps
ps
ꢀ
20ꢀ to 80ꢀ
NOTE 1: Please refer to the Phase Noise Plots following this section.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at VCCO/2.
NOTE 3: These parameters are guaranteed by characterization. Not tested in production.
843252AG-04
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REV.A JANUARY 25, 2006
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PRELIMINARY
ICS843252-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
2V
Phase Noise Plot
SCOPE
VCC,
Qx
VCCA,
VCCO
LVPECL
Phase Noise Mask
nQx
VEE
Offset Frequency
f1
f2
-1.3V 0.165V
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQx
Qx
80ꢀ
tF
80ꢀ
tR
VSWING
20ꢀ
Clock
Outputs
20ꢀ
nQy
Qy
tsk(o)
OUTPUT SKEW
OUTPUT RISE/FALL TIME
nQ0, nQ1
Q0, Q1
tPW
tPERIOD
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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REV.A JANUARY 25, 2006
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PRELIMINARY
ICS843252-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS843252-04 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. VCC, VCCA,
and VCCO should be individually connected to the power
supply plane through vias, and bypass capacitors should
be used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS843252-04 has been characterized with 18pF paral- parallel resonant crystal and were chosen to minimize the
lel resonant crystals.The capacitor values, C1 and C2, shown ppm error. The optimum C1 and C2 values can be slightly
in Figure 2 below were determined using a 25MHz, 18pF adjusted for different board layouts.
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
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REV.A JANUARY 25, 2006
6
PRELIMINARY
ICS843252-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVPECL OUTPUT
For applications not requiring the use of the crystal oscillator All unused LVPECL outputs can be left floating. We
input, both XTAL_IN and XTAL_OUT can be left floating. recommend that there is no trace attached. Both sides of the
Though not required, but for additional protection, a 1kΩ differential output pair should either be left floating or
resistor can be tied from XTAL_IN to ground.
terminated.
REF_CLK INPUT:
For applications not requiring the use of the reference clock,
it can be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the REF_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
TERMINATION FOR 3.3V LVPECL OUTPUT
The clock layout topology shown below is a typical termination
for LVPECL outputs. The two different layouts mentioned are
recommended only as guidelines.
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and minimize
signal distortion. Figures 3A and 3B show two different layouts
which are recommended only as guidelines. Other suitable clock
layouts may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs.Therefore, terminat-
ing resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
84Ω
84Ω
((VOH + VOL) / (VCC – 2)) – 2
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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REV.A JANUARY 25, 2006
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PRELIMINARY
ICS843252-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS843051.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS843051 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 80mA = 277.2mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 277.2mW + 60mW = 337.2mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 81.8°C/W per Table 6 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.337W * 81.8°C/W = 97.6°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 6.THERMAL RESISTANCE θJA FOR 16 LEADTSSOP, FORCED CONVECTION
θJA by Velocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
843252AG-04
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REV.A JANUARY 25, 2006
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PRELIMINARY
ICS843252-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 3.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 3. LVPECL DRIVER CIRCUIT ANDT ERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW L
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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REV.A JANUARY 25, 2006
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PRELIMINARY
ICS843252-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOWT ABLE FOR 16 LEAD TSSOP
θ
JA by Velocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS843252-04 is: 2210
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PRELIMINARY
ICS843252-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 16 LEADTSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum Maximum
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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REV.A JANUARY 25, 2006
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PRELIMINARY
ICS843252-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
3.3V LVPECL CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS843252AG-04
ICS843252AG-04T
ICS843252AG-04LF
ICS843252AG-04LFT
43252A04
43252A04
3252A04L
3252A04L
16 Lead TSSOP
16 Lead TSSOP
2500 tape & reel
tube
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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REV.A JANUARY 25, 2006
10
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