ICS84329BY [ICSI]
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER; 700MHZ ，低抖动，水晶- TO- 3.3V的差分LVPECL频率合成器
| 型号： | ICS84329BY |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总19页 (文件大小：235K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
The ICS84329B is a general purpose, single • Fully integrated PLL, no external loop filter requirements
ICS
HiPerClockS™
output high frequency synthesizer and a
member of the HiPerClockS™ family of High
• Parallel resonant crystal oscillator interface
Performance Clock Solutions from ICS. The
• One differential 3.3V LVPECL output
• Output frequency range: 31.25MHz to 700MHz
• VCO range: 250MHz to 700MHz
• Parallel interface for programming counter
and output dividers during power-up
VCO operates at a frequency range of 250MHz
to 700MHz.TheVCO frequency is programmed in steps equal
to the value of the crystal frequency divided by 16.The VCO
and output frequency can be programmed using the serial or
parallel interfaces to the configuration logic. The output can
be configured to divide the VCO frequency by 1, 2, 4, and 8.
Output frequency steps as small as 125kHz to 1MHz
can be achieved using a 16MHz crystal depending on the
output dividers.
• Serial 3 wire interface
• RMS Period jitter: 5.5ps (maximum)
• Cycle-to-cycle jitter: 35ps (maximuml)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
PIN ASSIGNMENT
BLOCK DIAGRAM
25 24 23 22 21 20 19
OE
S_CLOCK
26
18
N1
N0
M8
M7
M6
M5
M4
S_DATA
S_LOAD
27
28
1
17
16
15
14
13
12
XTAL_IN
OSC
XTAL_OUT
ICS84329B
28-Lead PLCC
V Package
VCCA
nc
÷ 16
2
11.6mm x 11.4mm x 4.1mm
TopView
nc
3
4
XTAL_IN
PLL
PHASE DETECTOR
÷1
÷2
÷4
÷8
5
6
7
8
9 10 11
1
0
FOUT
nFOUT
VCO
÷ M
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
32 31 30 29 28 27 26 25
24
1
2
3
4
5
6
7
8
S_CLOCK
S_DATA
S_LOAD
VCCA
nc
M0:M8
N0:N1
23
22
21
20
19
18
17
N1
N0
M8
M7
M6
M5
M4
ICS84329B
32-Lead LQFP
Y package
7mm x 7mm x 1.4mm
TopView
VCCA
nc
nc
XTAL_IN
9
10 11 12 13 14 15 16
84329BV
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REV.B JANUARY 18, 2006
1
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes op-
eration using a 16MHz crystal. Valid PLL loop divider values
N output divider. On the LOW-to-HIGH transition of the
nP_LOAD input, the data is latched and the M divider remains
for different crystal or input frequencies are defined in the In- loaded until the next LOW transition on nP_LOAD or until a
put Frequency Characteristics, Table 6, NOTE 1.
serial event occurs. The TEST output is Mode 000 (shift reg-
ister out) when operating in the parallel input mode.The rela-
tionship between the VCO frequency, the crystal frequency
The ICS84329B features a fully integrated PLL and therefore
requires no external components for setting the loop band-
width. A series-resonant, fundamental crystal is used as the
input to the on-chip oscillator. The output of the oscillator is
divided by 16 prior to the phase detector.With a 16MHz crys-
tal this provides a 1MHz reference frequency.The VCO of the
PLL operates over a range of 250MHz to 700MHz.The output
of the M divider is also applied to the phase detector.
fxtal
16
and the M divider is defined as follows:
x
fVCO =
M
The M value and the required values of M0 through M8
are shown in Table 3B, Programmable VCO Frequency
Function Table. Valid M values for which the PLL will
achieve lock are defined as 250 ≤ M ≤ 511. The frequency
out is defined as follows:
fVCO fxtal
M
N
fout
x
=
=
The phase detector and the M divider force the VCO output fre-
quency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the LVPECL
output buffers.The divider provides a 50% output duty cycle.
N
16
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the
shift register are loaded into the M divider when S_LOAD tran-
sitions from LOW-to-HIGH.The M divide and N output divide
values are latched on the HIGH-to-LOW transition of S_LOAD.
If S_LOAD is held HIGH, data at the S_DATA input is passed
directly to the M divider on each rising edge of S_CLOCK.
The serial mode can be used to program the M and N bits and
test bitsT2:T0.The internal registers T2:T0 determine the state
of the TEST output as follows:
The programmable features of the ICS84329B support two
input modes to program the M divider and N output divider.
The two input operational modes are parallel and serial. Fig-
ure 1 shows the timing diagram for each mode. In parallel mode
the nP_LOAD input is LOW. The data on inputs M0 through
M8 and N0 through N1 is passed directly to the M divider and
T2
0
0
T1
0
0
T0
0
1
TEST Output
Shift Register Out
fOUT
fOUT
fOUT
fOUT
High
0
1
0
PLL Reference Xtal ÷ 16
0
1
1
VCO ÷ M
(non 50% Duty M divider)
fOUT
1
0
0
fOUT
fOUT
fOUT
LVCMOS Output Frequency < 200MHz
1
1
0
1
1
0
Low
S_CLOCK ÷ M
(non 50% Duty Cycle M divider)
S_CLOCK ÷ N divider
1
1
1
fOUT ÷ 4
fOUT
S
ERIAL LOADING
S_CLOCK
T2
t
T1
T0
N1
N0
M8 M7 M6 M5 M4 M3 M2 M1 M0
S_DATA
S_LOAD
nP_LOAD
t
S
H
t
S
P
ARALLEL LOADING
M0:M8, N0:N1
nP_LOAD
M, N
t
t
H
S
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
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84329BV
REV.B JANUARY 18, 2006
2
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 1. PIN DESCRIPTIONS
Name
Type
Description
VCCA
Power
Analog supply pin.
XTAL_IN,
XTAL_OUT
Input
Crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Output enable. When logic HIGH, the outputs are enabled (default).
When logic LOW, the outputs are disabled and drive differential low:
FOUT = LOW, nFOUT = HIGH. LVCMOS / LVTTL interface levels.
Parallel load input. Determines when data present at M8:M0 is loaded into
M divider, and when data present at N1:N0 sets the N output divide value.
LVCMOS / LVTTL interface levels.
M divider inputs. Data latched on LOW-to-HIGH transistion of nP_LOAD input.
LVCMOS / LVTTL interface levels.
Determines N output divider value as defined in Table 3C Function Table.
LVCMOS / LVTTL interface levels.
OE
Input
Pullup
nP_LOAD
Input
Input
Pullup
M0, M1, M2, M3,
M4, M5, M6, M7, M8
Pullup
Pullup
N0, N1
VEE
Input
Power
Output
Negative supply pins.
Test output which is used in the serial mode of operation.
LVCMOS / LVTTL interface levels.
TEST
VCC
Power
Output
Core supply pins.
nFOUT, FOUT
Differential output for the synthesizer. 3.3V LVPECL interface levels.
Clocks the serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the M divider.
LVCMOS / LVTTL interface levels.
S_CLOCK
S_DATA
Input
Input
Input
Pulldown
Pulldown
Pulldown
S_LOAD
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
84329BV
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REV.B JANUARY 18, 2006
3
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
X
X
X
X
X
X
Reset. M and N bits are all set HIGH.
Data on M and N inputs passed directly to M divider and
N output divider. TEST mode 000.
L
↑
Data Data
Data Data
X
X
X
Data is latched into input registers and remains loaded
until next LOW transition or until a serial event occurs.
Serial input mode. Shift register is loaded with data on
S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are passed to the M divider
and N output divider.
L
L
↑
X
↑
L
X
H
H
X
X
X
X
Data
Data
H
H
X
X
X
X
↓
L
Data
X
M divide and N output divide values are latched.
Parallel or serial input do not affect shift registers.
L
X
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
1
64
M6
1
32
M5
1
16
M4
1
8
M3
1
4
M2
0
2
M1
1
1
M0
0
VCO Frequency
(MHz)
M Divide
250
251
252
253
•
250
251
252
253
•
0
1
1
1
1
1
0
1
1
0
1
1
1
1
1
1
0
0
0
1
1
1
1
1
1
0
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
509
510
511
509
510
511
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
0
1
1
1
1
1
1
1
1
1
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
N1
N0
0
Minimum
250
Maximum
700
0
0
1
1
1
2
4
8
1
125
350
0
62.5
175
1
31.25
87.5
84329BV
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REV.B JANUARY 18, 2006
4
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
37.8°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VCC
VCCA
ICC
Core Supply Voltage
3.135
3.135
3.3
3.3
3.465
3.465
125
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
ICCA
15
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VCC + 0.3
0.8
V
V
Input Low Voltage
Input High Current
-0.3
M0-M8, N0, N1,
OE, nP_LOAD
S_LOAD,
S_DATA, S_CLOCK
M0-M8, N0, N1,
OE, nP_LOAD
S_LOAD,
V
CC = VIN = 3.465V
VCC = VIN = 3.465V
CC = 3.465V, VIN = 0V
5
µA
µA
µA
µA
IIH
150
V
-150
IIL
Input Low Current
VCC = 3.465V, VIN = 0V
-5
S_DATA, S_CLOCK
VOH
VOL
Output High Voltage; NOTE 1
Output Low Voltage; NOTE 1
2.6
V
V
0.5
NOTE 1: Outputs terminated with 50Ω to VCC/2. See Parameter Measurement Information, 3.3V Output Load Test Circuit.
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50Ω to VCC - 2V.
84329BV
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REV.B JANUARY 18, 2006
5
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
10
25
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
fIN Input Frequency
Test Conditions
Minimum
Typical
Maximum
Units
MHz
MHz
XTAL; NOTE 1
S_CLOCK
10
25
50
NOTE 1: For the crystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency
range of 250MHz or 700MHz. Using the minimum frequency of 10MHz valid values of M are 400 ≤ M ≤ 511.
Using the maximum frequency of 25MHz valid values of M are 160 ≤ M ≤ 448.
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
FOUT
Output Frequency
700
5.5
12
MHz
ps
fOUT ≥ 65MHz
fOUT < 65MHz
fOUT ≥ 50MHz
fOUT < 50MHz
20% to 80%
tjit(per)
Period Jitter, RMS; NOTE 1, 2
Cycle-to-Cycle Jitter; NOTE 1, 2
ps
35
ps
tjit(cc)
50
ps
tR / tF
tS
Output Rise/Fall Time
Setup Time
300
5
800
ps
ns
tH
Hold Time
5
ns
tL
PLL Lock Time
Output Duty Cycle
10
55
ms
%
odc
45
50
See Parameter Measurement Information section.
Characterized using a 16MHz XTAL.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65
NOTE 2: See Applications section.
84329BV
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REV.B JANUARY 18, 2006
6
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
SCOPE
nFOUT
FOUT
VCC
VCCA
,
Qx
LVPECL
➤
➤
tcycle n
tcycle n+1
➤
➤
nQx
VEE
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
CYCLE-TO-CYCLE JITTER
VOH
VREF
nFOUT
FOUT
tPW
tPERIOD
VOL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
tPW
odc =
x 100%
tPERIOD
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
S_DATA
tHOLD
S_CLOCK
S_LOAD
tSET-UP
80%
80%
VSWING
20%
Clock
20%
tSET-UP
Outputs
tF
tR
M0:M8
N0:N1
tHOLD
nP_LOAD
tSET-UP
OUTPUT RISE/FALL TIME
SETUP AND HOLD
84329BV
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REV.B JANUARY 18, 2006
7
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84329B provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS84329B has been characterized with 18pF parallel parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
resonant crystals. The capacitor values, C1 and C2, shown
in Figure 3 below were determined using a 25MHz, 18pF
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 3. CRYSTAL INPUt INTERFACE
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
84329BV
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REV.B JANUARY 18, 2006
8
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
14
12
10
8
6
4
2
0
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525
Output Frequency (MHz)
FIGURE 4A. RMS JITTER VS. fOUT (using a 16MHz XTAL)
60
50
40
30
20
10
0
25 50 75 100 125 150 175 200 225 250 275 300 325 350 375 400 425 450 475 500 525
Output Frequency (MHz)
FIGURE 4B. CYCLE-TO-CYCLE JITTER VS. fOUT (using a 16MHz XTAL)
84329BV
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REV.B JANUARY 18, 2006
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
LAYOUT GUIDELINE
The schematic of the ICS84329B layout example used in this
layout guideline is shown in Figure 5A. The ICS84329B recom- nent types, the density of the components, the density of the
layout in the actual system will depend on the selected compo-
traces, and the stack up of the P.C. board.
mended PCB board layout for this example is shown in Figure
5B. This layout example is used as a general guideline. The
C3
22p
16MHz,18pF
X1
VCC
VCC=3.3V
C4
22p
R7
10
SP = Space (i.e. not intstalled)
M4
12
13
14
15
16
17
18
4
M4
M5
M6
M7
M8
N0
N1
XTALIN
3
M5
M6
M7
M8
N2
N1
M [8:0]= 110010000 (400)
N[1:0] =01 (Divide by 2)
nc
2
nc
1
VCCA
VCCA
28
S_LOAD
27
S_DATA
26
C11
0.01u
C16
10u
S_CLOCK
U1
84329BV
C1
VCC
0.1uF
Zo = 50 Ohm
Fout = 200 MHz
RU0
SP
RU1
SP
RU7
1K
RU8
1K
RU9
SP
RU10
1K
RU11
SP
RU12
1K
C2
0.1u
Zo = 50 Ohm
R2
50
R1
50
RD0
1K
RD1
1K
RD7
SP
RD8
SP
RD9
1K
RD10
SP
RD6
1K
RD12
SP
R3
50
FIGURE 5A. SCHEMATIC OF RECOMMENDED LAYOUT FOR 28 LEAD PLCC
84329BV
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REV.B JANUARY 18, 2006
10
ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
• The differential 50Ω output traces should have the
same length.
The following component footprints are used in this layout
example:
• Avoid sharp angles on the clock trace.Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C1, C2 and C3, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling
capacitor and the power pin caused by the via.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace
widths between the differential clock trace and the other
signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors.This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
CLOCK TRACES AND TERMINATION
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location.While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
4 (XTAL_IN) and 5 (XTAL_OUT). The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted para-
sitic inductance and capacitance. Other signal traces should not
be routed near the crystal traces.
X1
C3
C4
U1
GND
VCC
PIN 2
PIN 1
C16
C11
R7
VCCA
VIA
VCCA
Signals
Traces
C1
C2
50 Ohm
Traces
FIGURE 5B. PCB BOARD LAYOUT FOR ICS84329B 28 LEAD PLCC
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina- designed to drive 50Ω transmission lines. Matched imped-
tion for LVPECL outputs.The two different layouts mentioned ance techniques should be used to maximize operating
are recommended only as guidelines.
frequency and minmize signal distortion. Figures 6A and
6B show two different layouts which are recommended only
FOUT and nFOUT are low impedance follower outputs that as guidelines.Other suitable clock layouts may exist and it
generate ECL/LVPECL compatible outputs. Therefore, ter- would be recommended that the board designers simulate
minating resistors (DC current path to ground) or current to guarantee compatibility across all printed circuit and clock
sources must be used for functionality. These outputs are component process variations.
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 6A. LVPECL OUTPUTTERMINATION
FIGURE 6B. LVPECL OUTPUTT ERMINATION
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84329B.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84329B is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 140mA = 485mW
Power (outputs)MAX = 30mW/Loaded Output pair
Total Power_MAX (3.465V, with all outputs switching) = 485mW + 30mW = 515mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 31.1°C/W perTable 8A below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.515W * 31.1°C/W = 86°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 8A. THERMAL RESISTANCE θJA FOR 28-PIN PLCC, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 8B. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θJA byVelocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
84329BV
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the Figure 7.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 7. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, VOUT = V
= V
– 0.9V
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
L
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V – (V - 2V))/R ] * (V
))
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
84329BV
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 9A. θJAVS. AIR FLOW TABLE FOR 28 LEAD PLCC
θJA byVelocity (Linear Feet per Minute)
0
200
500
Multi-Layer PCB, JEDEC Standard Test Boards
37.8°C/W
31.1°C/W
28.3°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TABLE 9B. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84329B is: 4408
Pin compatible with the MC12429
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - V SUFFIX FOR 28 LEAD PLCC
TABLE 10A. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
SYMBOL
MINIMUM
MAXIMUM
N
A
28
4.19
2.29
4.57
3.05
A1
A2
b
1.57
2.11
0.33
0.53
c
0.19
0.32
D
12.32
11.43
4.85
12.57
11.58
5.56
D1
D2
E
12.32
11.43
4.85
12.57
11.58
5.56
E1
E2
Reference Document: JEDEC Publication 95, MS-018
84329BV
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX 32 LEAD LQFP
TABLE 10B. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
84329BV
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 11. ORDERING INFORMATION
Part/Order Number
ICS84329BV
Marking
Package
Shipping Packaging Temperature
ICS84329BV
ICS84329BV
28 Lead PLCC
Tube
500 Tape & Reel
Tube
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS84329BVT
ICS84329BVLF
ICS84329BVLFT
ICS84329BY
28 Lead PLCC
ICS84329BVLF
ICS84329BVLF
ICS84329BY
28 Lead "Lead-Free" PLCC
28 Lead "Lead-Free" PLCC
32 Lead LQFP
500 Tape & Reel
Tray
ICS84329BYT
ICS84329BYLF
ICS84329BYLFT
ICS84329BY
32 Lead LQFP
1000 Tape & Reel
Tray
ICS84329BYLF
ICS84329BYLF
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP
1000 Tape & Reel
NOTE: Parts thar are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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ICS84329B
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
REVISION HISTORY SHEET
Description of Change
Rev
Table
Page
Date
1
Features Section - added "Parallel resonant" to crystal bullet.
A
12/15/04
1
Features Section - corrected Output frequency range from 25MHz to
31.25MHz. Added Lead-Free bullet.
B
B
2
6
17
8
8
Updated Parallel & Serial Load Operations.
Crystal Table - added Drive Level.
Ordering Information Table - added Lead-Free part numbers and note.
Power Supply Filtering Techniques - added ferrite bead sentence.
Added Recommendations for Unused Input and Output Pins.
Ordering Information Table - added Lead-Free marking.
6/10/05
1/18/06
T5
T11
T11
18
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