ICS8432AY-51LFT [IDT]
Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32;
| 型号： | ICS8432AY-51LFT |
| 厂家： | 
INTEGRATED DEVICE TECHNOLOGY |
| 描述： | Clock Generator, 700MHz, PQFP32, 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-32 时钟 外围集成电路 晶体 |
| 文件： | 总16页 (文件大小：166K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8432-51
Integrated
Circuit
Systems, Incꢀ
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8432-51 is a general purpose, dual output • Dual differential 3.3V LVPECLoutput
Crystal-to-3.3V Differential LVPECLHigh Frequency
Synthesizer and a member of the HiPerClockS™
family of High Performance Clocks Solutions from
ICS. The ICS8432-51 has a selectable TEST_CLK
• Selectable crystal oscillator interface or LVCMOS
TEST_CLK
HiPerClockS™
• TEST_CLK can accept the following input levels:
or crystal inputs. The TEST_CLK input accepts LVCMOS or
LVTTLinput levels and translates them to 3.3V LVPECL levels.
The VCO operates at a frequency range of 200MHz to
700MHz. The VCO frequency is programmed in steps equal
to the value of the input reference or crystal frequency.
The VCO and output frequency can be programmed using
the serial or parallel interfaces to the configuration logic.
The low phase noise characteristics of the ICS8432-51 makes
it an ideal clock source for Gigabit Ethernet, Fiber Channel 1 and
2, and Infiniband applications.
LVCMOS or LVTTL
• Maximum output frequency up to 700MHz
• Maximum crystal or TEST_CLK input frequency up to
25MHz
• VCO range: 200MHz to 700MHz
• Parallel or serial interface for programming counter and
output dividers
• RMS period jitter: TBDps (typical)
• Cycle-to-cycle jitter: 30ps (typical)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_SEL
TEST_CLK
0
32 31 30 29 28 27 26 25
XTAL1
1
M5
OSC
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL1
XTAL2
M6
M7
M8
N0
N1
nc
TEST_CLK
XTAL_SEL
VCCA
ICS8432-51
S_LOAD
S_DATA
S_CLOCK
MR
PLL
PHASE DETECTOR
MR
0
1
VEE
VCO
FOUT0
nFOUT0
FOUT1
nFOUT1
÷ N
9
10 11 12 13 14 15 16
÷ M
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
CONFIGURATION
INTERFACE
LOGIC
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
M0:M8
N0:N1
Y Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8432AY-51
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REV. A AUGUST 20, 2001
1
PRELIMINARY
ICS8432-51
Integrated
Circuit
Systems, Incꢀ
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes operation using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input Frequency Characteristics, Table 6, NOTE 1.
The ICS8432-51 features a fully integrated PLL and therefore requires no external components for setting the loop bandwidth.
A fundamental crystal is used as the input to the on-chip oscillator. The output of the oscillator is fed into the phase detector.
A 25MHz crystal provides a 25MHz phase detector reference frequency. The VCO of the PLL operates over a range of
200MHz to 700MHz. The output of the loop divider is also applied to the phase detector.
The phase detector and the loop filter divider force the VCO output frequency to be M times the reference frequency by
adjusting the VCO control voltage. Note that for some values of M (either too high or too low) the PLL will not achieve lock. The
output of the VCO is scaled by a divider prior to being sent to each of the LVPECL output buffers. The divider provides a 50%
output duty cycle.
The programmable features of the ICS8432-51 support two input modes and programmable PLL loop divider and output
divider. The two input operational modes are parallel and serial. Figure 1 shows the timing diagram for each mode. In parallel
mode the nP_LOAD input is initially LOW. The data on inputs M0 through M8 and N0 and N1 is passed directly to the ripple
counter. On the LOW-to-HIGH transition of the nP_LOAD input the data is latched and the ripple counter remains loaded until
the next LOW transition on nP_LOAD or until a serial event occurs. As a result the M and N bits can be hardwired to set the
ripple counter to a specific default state that will automatically occur during power-up. The TEST output is LOW when operat-
ing in the parallel input mode. The relationship between the VCO frequency, the crystal frequency and the loop divider is
defined as follows:
fVCO = fxtal x M
The M count and the required values of M0 through M8 are shown in Table 4B, Programmable VCO Frequency Function.
Valid M values for which the PLL will achieve lock for a 25MHz reference are defined as 8 ≤ M ≤ 28. The frequency out is
defined as follows:
FOUT = fVCO = fxtal x M
N
N
Serial operation occurs when nP_LOAD is HIGH and S_LOAD is LOW. The shift register is loaded by sampling the
S_DATA bits with the rising edge of S_CLOCK. The contents of the shift register are loaded into the ripple counter when
S_LOAD transitions from LOW-to-HIGH. The ripple counter divide values are latched on the HIGH-to-LOW transition of
S_LOAD. If S_LOAD is held HIGH data at the S_DATA input is passed directly to the ripple counter on each rising edge of
S_CLOCK. The serial mode can be used to program the M and N bits and test bits T1 and T0. The internal registers T0 and T1
determine the state of the TEST output as follows:
T1 T0
TEST Output
LOW
0
0
1
1
0
1
0
1
S_Data
Output of M divider
CMOS Fout
T1
T0
*NULL
N1
N0
M8
M7
M6
M5
M4
M3
M2
M1
M0
S_DATA
S_CLOCK
S_LOAD
M0:M8, N0:N1
nP_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
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REV. A AUGUST 20, 2001
2
PRELIMINARY
ICS8432-51
Integrated
Circuit
Systems, Incꢀ
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
1
M5
Input
Input
M counter/divider inputs. Data latched on LOW-to-HIGH transistion
of nP_LOAD input. LVCMOS / LVTTL interface levels.
2, 3, 4,
28, 29,
30, 31, 32
M6, M7, M8,
M0, M1,
M2, M3, M4
Pulldown
Pulldown
Determines output divider value as defined in Table 4C Function
table. LVCMOS / LVTTL interface levels.
5, 6
N0, N1
Input
7
nc
Unused
Power
No connect.
8, 16
VEE
Negative supply pins. Connect to ground.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS interface levels.
9
TEST
VCC
Output
Power
Output
Power
Output
10
Positive supply pin.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
11, 12
13
FOUT1, nFOUT1
VCCO
Output supply pin. Connect to 3.3V.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
14, 15
FOUT0, nFOUT0
Forces outputs LOW, but does not effect loaded M, N, and T
values. LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
on the rising edge of S_CLK.
Shift register serial input. Data sampled on the rising edge of
S_CLK.
17
18
19
MR
Input
Input
Input
Pulldown
Pulldown
Pulldown
Pulldown
S_CLOCK
S_DATA
Controls transition of data from shift register into the ripple counter.
LVCMOS / LVTTL interface levels.
20
21
S_LOAD
VCCA
Input
Power
Analog supply pin. Connect to 3.3V.
Selects between crystal or test inputs as the PLL reference
source. LVCMOS / LVTTL interface levels. Selects XTAL inputs
when HIGH. Selects TEST_CLK when LOW.
22
XTAL_SEL
Input
Pullup
23
TEST_CLK
Input
Input
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
Crystal oscillator inputs.
24, 25
XTAL1, XTAL2
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into ripple counter, and when data present at N1:N0 sets
the output divide value. LVCMOS / LVTTL interface levels.
26
27
nP_LOAD
VCO_SEL
Input
Input
Determines whether synthesizer is in PLL or bypass mode.
Pullup
LVCMOS / LVTTL interface levels.
NOTE: Pullup and Pulldown refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
8432AY-51
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REV. A AUGUST 20, 2001
3
PRELIMINARY
ICS8432-51
Integrated
Circuit
Systems, Incꢀ
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
Input Pulldown Resistor
4
pF
KΩ
KΩ
RPULLUP
RPULLDOWN
51
51
TABLE 3A. PARALLEL AND SERIAL MODE FUNCTION TABLE
Inputs
Conditions
Reset. M and N counters reset.
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Data on M and N inputs passed directly to the
ripple counter and output divider.
TEST output forced LOW.
Data is latched into input registers and remains
loaded until next LOW transition or until a serial
event occurs.
L
L
Data Data
Data Data
X
X
X
L
↑
L
X
X
Serial input mode. Shift register is loaded with
data on S_DATA on each rising edge of
S_CLOCK.
Contents of the shift register are passed to the
ripple counter and output divider.
Ripple counter and output divide values are
latched.
L
L
H
H
X
X
X
X
L
↑
Data
Data
↑
L
L
L
H
H
X
X
X
X
↓
L
Data
X
L
X
Parallel or serial input do not affect shift registers.
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
0
8
M3
1
4
M2
0
2
M1
0
1
M0
0
VCO Frequency
(MHz)
M Count
200
225
250
275
•
8
9
0
0
0
0
0
1
0
0
1
10
11
•
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
675
700
26
27
28
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
1
0
0
NOTE 1: These M count values and the resulting frequency correspond to crystal or test clock input frequency of 25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
Output Frequency (MHz)
N Divider Value
N1
0
N0
0
Minimum
Maximum
700
1
2
4
8
200
100
50
0
1
350
1
0
175
1
1
25
87.5
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REV. A AUGUST 20, 2001
4
PRELIMINARY
ICS8432-51
Integrated
Circuit
Systems, Incꢀ
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCCX
Inputs, VCC
Outputs, VCCO
4.6V
-0.5V to VCC + 0.5 V
-0.5V to VCCO + 0.5V
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, TSTG -65°C to 150°C
Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only. Functional operation of product at these conditions or any conditions beyond those listed in the DC
Characteristics or AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods may
affect product reliability.
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
3.465
3.465
3.465
110
V
V
VCCA
VCCO
IEE
3.135
3.3
3.135
3.3
V
mA
TABLE 5B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
Input
VIH
All input pins, except for
High Voltage XTAL1 and XTAL2
2
VCC + 0.3
0.8
V
V
Input
Low Voltage XTAL1 and XTAL2
M0-M4, M6-M8, N0, N1, MR,
All input pins, except for
VIL
-0.3
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
*VCCx = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
M5, XTAL_SEL, VCO_SEL
VCCx = VIN = 3.465V
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
VCCx = 3.465V,
-5
VIN = 0V
Input
Low Current
IIL
VCCx = 3.465V,
VIN = 0V
M5, XTAL_SEL, VCO_SEL
-150
2.6
µA
V
VCCx = 3.135V,
IOH = -36mA
Output
High Voltage
VOH
VOL
TEST
TEST
VCCx = 3.135V,
IOL = 36mA
Output
Low Voltage
0.5
V
*NOTE 1: VCCx denotes VCC, VCCA, and VCCO
.
8432AY-51
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REV. A AUGUST 20, 2001
5
PRELIMINARY
ICS8432-51
Integrated
Circuit
Systems, Incꢀ
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
TABLE 5C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 2.1
VCCO - 2.0
0.6
VCCO - 1.0
VCCO -1.6
0.85
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V.
TABLE 6. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
TEST_CLK; NOTE 1
XTAL1, XTAL2; NOTE 1
S_CLOCK
12
12
25
25
50
MHz
MHz
MHz
Maximum
fIN
Input Frequency
NOTE 1: For the input crystal and TEST_CLK frequency range the M value must be set for the VCO to operate within the
200MHz to 700MHz range. Using the minimum input frequency of 12MHz valid values of M are 17 ≤ M ≤ 58. Using the
maximum frequency of 25MHz valid values of M are 8 ≤ M ≤ 28.
TABLE 7. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Fundamental
Frequency
12
50
25
80
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
pF
nH
°C
Series Pin Inductance
Operating Temperature Range
3
0
7
70
TABLE 8. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V±5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
tjit(cc)
tjit(per)
tsk(o)
tR
Maximum Output Frequency
25
700
MHz
ps
Cycle-to-Cycle Jitter, RMS; NOTE 1, 3
Period Jitter, RMS; NOTE 1, 3
Output Skew; NOTE 2, 3
Output Rise Time
30
ps
10
700
700
5
ps
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
ps
tF
Output Fall Time
ps
M, N to nP_LOAD
ns
tS
Setup Time
Hold Time
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
5
5
ns
tH
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
odc
Output Duty Cycle
PLL Lock Time
47
53
10
%
tLOCK
ms
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Jitter performance using Xtal inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
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REV. A AUGUST 20, 2001
6
PRELIMINARY
ICS8432-51
Integrated
Circuit
Systems, Incꢀ
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCC, VCCA, VCCO
SCOPE
Qx
LVPECL
VCC, VCCA, VCCO = 2.0V
nQx
VEE = -1.3V ± 0.135V
FIGURE 1 - 3.3V OUTPUT LOAD TEST CIRCUIT
nFOUTx
FOUTx
nFOUTy
FOUTy
tsk(o)
FIGURE 2 - OUTPUT SKEW
80%
80%
VSWING
20%
20%
Clock Inputs
and Outputs
tR
tF
FIGURE 3 - INPUT AND OUTPUT RISE AND FALL TIME
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PRELIMINARY
ICS8432-51
Integrated
Circuit
Systems, Incꢀ
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
nFOUTx
TEST, FOUTx
Pulse Width
tPERIOD
tPW
tPERIOD
odc =
FIGURE 4 - odc & tPERIOD
IDEAL OUTPUT
VOH
V
ref
VOL
➤
➤
1
fo
➤
➤
ACTUALOUTPUT
VOH
V
ref
VOL
tcycle n
where fo is the nominal output frequency and
tcycle n is any cycle within the sample measured
on controlled edges
tjit(per) = tcycle n - 1
fo
FIGURE 5 - Period Jitter
nFOUTx
FOUTx
➤
➤
tcycle n+1
tcycle n
➤
➤
tjit(cc) = tcycle n –tcycle n+1
FIGURE 6 - Cycle-to-Cycle Jitter
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REV. A AUGUST 20, 2001
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PRELIMINARY
ICS8432-51
Integrated
Circuit
Systems, Incꢀ
700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
APPLICATIONS
STORAGE AREA NETWORKS
Avariety of technologies are used for interconnection of the elements within a SAN. The tables below lists the common frequencies
used as well as the settings for the ICS8432-51 to generate the appropriate frequency.
Table 9. Common SANs Applications Frequencies
Reference Freq. to SERDES
(MHz)
Crystal Frequency
(MHz)
Interconnect Technology
Gigabit Ethernet
Fibre Channel
Clock Rate
1.25 GHz
125, 250, 156.25
106.25, 53.125, 132.81
125, 250
25, 25, 19.53
16.6, 25, 26.563
25, 25
FC1 1.0625 GHz
FC2 2.1250 GHz
Infiniband
2.5 GHz
Table 10. Configuration Details for SANs Applications
ICS8432-01
ICS8432-51
Interconnect
Technology
Crystal Frequency
(MHz)
Output Frequency
to SERDES
(MHz)
M & N Settings
M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N0
25
25
125
250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
1
1
1
0
0
1
1
0
0
0
0
1
1
0
0
0
0
0
0
0
0
1
1
0
0
0
0
1
1
0
0
0
1
1
0
0
0
1
0
1
1
1
0
0
0
0
0
0
1
0
1
1
0
Gigabit Ethernet
19.53
25
156.25
53.125
106.25
132.81
125
Fiber Channel 1
Fiber Channel 2
Infiniband
25
16.6
25
25
250
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8432-51 provides
separate power supplies to isolate any high switching noise
from the outputs to the internal PLL. VCC, VCCA, and VCCO should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, better power supply
isolation is required. Figure 7 illustrates how a 10Ω along with
a 10µF and a .01µF bypass capacitor should be connected to
each power supply pin.
3.3V
VCC
.01µF
.01µF
10Ω
VCCA
10 µF
FIGURE 7. POWER SUPPLY FILTERING
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8432AY-51
9
PRELIMINARY
ICS8432-51
Integrated
Circuit
Systems, Incꢀ
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
TERMINATION FOR LVPECL OUTPUTS
drive 50Ω transmission lines. Matched impedance techniques
should be used to maximize operating frequency and mini-
mize signal distortion. There are a few simple termination
schemes. Figures 8A and 8B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs. The two different layouts mentioned
are recommended only as guidelines.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, termi-
nating resistors (DC current path to ground) or current sources
must be used for functionality. These outputs are designed to
3.3V
Zo = 50Ω
Zo = 50Ω
5
2
5
Zo
Zo
2
FIN
FOUT
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
50Ω
Zo = 50Ω
FOUT
FIN
50Ω
➤
Zo = 50Ω
VCC - 2V
Zo = 50Ω
RTT
1
3
2
3
Zo
RTT =
Zo
Zo
2
(VOH + VOL / VCC –2) –2
FIGURE 8A. LVPECL OUTPUT TERMINATION
FIGURE 8B. LVPECL OUTPUT TERMINATION
LAYOUT GUIDELINE
The schematic of the ICS8432-51 layout example used in this layout guideline is shown in Figure 9A. The ICS8432-51 recommended
PCB board layout for this example is shown in Figure 9B. This layout example is used as a general guideline. The layout in the actual
system will depend on the selected component types, the density of the components, the density of the traces, and the stacking of
the P.C. board.
X1
R7
VCC
U1
10
C11
1
24
23
22
21
20
19
18
17
0.01u
C16
10u
M5
M6
M7
M8
N0
N1
nc
XTAL1
REF_IN
nXTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
REF_IN
XTAL_SEL
2
3
4
5
6
7
8
S_LOAD
S_DATA
S_CLOCK
MR
VEE
Termination A
Termination
B (Not shown
in the layout)
VCC
8432-01
IN+
R1
R3
125
125
Zo = 50 Ohm
IN+
IN-
IN-
TL1
Zo = 50 Ohm
R2
50
R1
50
C14
0.1u
C15
0.1u
TL2
R2
84
R4
84
R3
50
FIGURE 9A. RECOMMENDED SCHEMATIC LAYOUT
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700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
The following component footprints are used in this layout
example: All the resistors and capacitors are size 0603.
traces should be routed first and should be locked prior to routing
other signals traces.
• The traces with 50Ω transmission lines TL1 and TL2 at
FOUT and nFOUT should have equal delay and run ad-
jacent to each other.Avoid sharp angles on the clock trace.
Sharp angle turns cause the characteristic impedance to
change on the transmission lines.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15 as close as pos-
sible to the power pins. If space allows, placing the decoupling
capacitor at the component side is preferred. This can reduce
unwanted inductance between the decoupling capacitor and the
power pin generated by the via.
• Keep the clock trace on same layer. Whenever possible,
avoid any vias on the clock traces. Any via on the trace
can affect the trace characteristic impedance and hence
degrade signal quality.
Maximize the pad size of the power (ground) at the decoupling
capacitor. Maximize the number of vias between power (ground)
and the pads. This can reduce the inductance between the power
(ground) plane and the component power (ground) pins.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow more space between the clock trace
and the other signal trace.
If VCCA shares the same power supply with VCC, insert the RC
filter R7, C11, and C16 in between. Place this RC filter as close
to the VCCA as possible.
• Make sure no other signal trace is routed between the
clock trace pair.
CLOCK TRACES AND TERMINATION
The matching termination resistors R1, R2, R3 and R4 should be
located as close to the receiver input pins as possible. Other termi-
nation scheme can also be used but is not shown in this example.
The component placements, locations and orientations should
be arranged to achieve the best clock signal quality. Poor clock
signal quality can degrade the system performance or cause
system failure. In the synchronous high-speed digital system,
the clock signal is less tolerable to poor signal quality than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The trace shape and the trace
delay might be restricted by the available space on the board and
the component location. While routing the traces, the clock signal
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL1) and 25 (XTAL2). The trace length between the X1
and U1 should be kept to a minimum to avoid unwanted parasitic
inductance and capacitance. Other signal traces should not be
routed near the crystal traces.
X1
GND
VCC
VIA
U1
PIN 1
C11
C16
VCCA
R7
Close to the input
pins of the
receiver
R4
R3
TL1N
C15
C14
TL1
R2
R1
TL1, TL2 are 50 Ohm traces and
equal length
FIGURE 9B. PCB BOARD LAYOUT FOR ICS8432-51
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PRELIMINARY
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Integrated
Circuit
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700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8432-51.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8432-51 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 110mA = 381.2mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30.2mW = 60.4mW
Total Power_MAX (3.465V, with all outputs switching) = 381.2mW + 60.4mW = 441.6mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = junction-to-ambient thermal resistance
Pd_total = Total device power dissipation (example calculation is in section 1 above)
TA =Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 11 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.441W * 42.1°C/W = 88.6°C. This is well below the limit of 125°C
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
Table 11. Thermal Resistance qJA for 32-pin LQFP, Forced Convection
qJA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 10.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 10 - LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage of V - 2V.
CC
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
Pd_H = [(V
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
)
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
L
– (V
- 2V))/R ] * (V
- V
)
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
L
•
•
For logic high, V = V
= V
– 1.0V
OUT
OH_MAX
CCO_MAX
Using V
= 3.465, this results in V
= 2.465V
= 1.765V
CCO_MAX
OH_MAX
For logic low, V = V
= V
– 1.7V
OUT
OL_MAX
CCO_MAX
Using V
= 3.465, this results in V
OL_MAX
CCO_MAX
Pd_H =[(2.465V - (3.465V - 2V))/50Ω] * (3.465V - 2.465V) = 20mW
Pd_L =[(1.765V - (3.465V - 2V))/50Ω] * (3.465V - 1.765V) = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
8432AY-51
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PRELIMINARY
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Integrated
Circuit
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700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 12. θJAVS. AIR FLOW TABLE
qJA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8432-51 is: 3703
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PRELIMINARY
ICS8432-51
Integrated
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700MHZ, CRYSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
PACKAGE OUTLINE -Y SUFFIX
TABLE 13. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
q
--
0
°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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PRELIMINARY
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Integrated
Circuit
Systems, Incꢀ
700MHZ, CYRSTAL-TO-3.3V DIFFERENTIAL
LVPECLFREQUENCY SYNTHESIZER
TABLE 14. ORDERING INFORMATION
Part/Order Number
ICS8432AY-51
Marking
Package
32 Lead LQFP
Count
250 per tray
1000
Temperature
0°C to 70°C
0°C to 70°C
ICS8432AY-51
ICS8432AY-51
ICS8432AY-51T
32 Lead LQFP on Tape and Reel
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
8432AY-51
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