ICS8432CY-11 [ICSI]
700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER; 700MHZ / 350MHZ ，低相位噪声， CRYSTAL - TO- 3.3V LVPECL频率合成器
| 型号： | ICS8432CY-11 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 700MHZ/350MHZ, LOW PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总16页 (文件大小：187K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS8432-11
Integrated
Circuit
Systems, Inc.
700MHZ/350MHZ, LOW PHASE NOISE,
CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS8432-11 is a general purpose, dual output
• Dual differential 3.3V LVPECL outputs
ICS
Crystal-to-3.3V Differential LVPECL High Frequency
• Selectable crystal oscillator interface or
LVCMOS/LVTTLTEST_CLK
HiPerClockS™
Synthesizer and a member of the HiPerClockS™
family of High Performance Clock Solutions from
ICS.The ICS8432-11 has a selectable TEST_CLK
• TEST_CLK can accept the following input levels:
LVCMOS or LVTTL
or crystal inputs. The TEST_CLK input accepts LVCMOS or
LVTTL input levels and translates them to 3.3V LVPECL
levels. The VCO operates at a frequency range of 200MHz
to 700MHz. The VCO frequency is programmed in steps
equal to the value of the input reference or crystal frequency.
Output frequencies up to 700MHz for FOUT and 350MHz
for FOUT/2 can be programmed using the serial or parallel
interfaces to the configuration logic. The low phase noise
characteristics and the multiple frequency outputs of the
ICS8432-11 makes it an ideal clock source for Fiber Channel
1 and 2, and Infiniband applications.
• Maximum FOUT frequency: 700MHz
• Maximum FOUT/2 frequency: 350MHz
• VCO range: 200MHz to 700MHz
• Parallel interface for programming counter and
VCO frequency multiplier and dividers
• Cycle-to-cycle jitter: 25ps (maximum)
• RMS period jitter: TBD
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
BLOCK DIAGRAM
PIN ASSIGNMENT
VCO_SEL
XTAL_SEL
TEST_CLK
XTAL_IN
32 31 30 29 28 27 26 25
M5
M6
M7
M8
N0
N1
nc
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
XTAL_IN
TEST_CLK
XTAL_SEL
VCCA
XTAL_OUT
ICS8432-11
S_LOAD
S_DATA
S_CLOCK
MR
VEE
MR
FOUT
9
10 11 12 13 14 15 16
nFOUT
FOUT/2
nFOUT/2
S_LOAD
S_DATA
S_CLOCK
nP_LOAD
TEST
32-Lead LQFP
7mm x 7mm x 1.4mm package body
Y Package
TopView
M0:M8
N0:N1
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
8432CY-11
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REV. E MAY 20, 2005
1
PRELIMINARY
ICS8432-11
Integrated
Circuit
Systems, Inc.
700MHZ/350MHZ, LOW PHASE NOISE,
CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes nP_LOAD or until a serial event occurs. As a result, the M and
operation using a 25MHz clock input. Valid PLL loop divider N bits can be hardwired to set the M divider and N output divider
values for different input frequencies are defined in the Input to a specific default state that will automatically occur during
Frequency Characteristics, Table 5, NOTE 1.
power-up.TheTEST output is LOW when operating in the paral-
lel input mode. The relationship between the VCO frequency,
The ICS8432-11 features a fully integrated PLL and there- the input frequency and the M divider is defined as follows:
fore requires no external components for setting the loop
bandwidth. A differential clock input is used as the input to the
fVCO = fxtal x M
ICS8432-11.This input is fed into the phase detector.A 25MHz The M value and the required values of M0 through M8 are
clock input provides a 25MHz phase detector reference fre- shown in Table 3B, Programmable VCO Frequency Function
quency.The VCO of the PLL operates over a range of 200MHz Table. Valid M values for which the PLL will achieve lock are
to 700MHz. The output of the M divider is also applied to the defined as 8 ≤ M ≤ 28.The frequency out is defined as follows:
phase detector.
fOUT = fVCO = fxtal x M
N
N
The phase detector and the M divider force the VCO output Serial operation occurs when nP_LOAD is HIGH and S_LOAD
frequency to be M times the reference frequency by adjust- is LOW.The shift register is loaded by sampling the S_DATA
ing the VCO control voltage. Note, that for some values of M bits with the rising edge of S_CLOCK. The contents of the
(either too high or too low), the PLL will not achieve lock. The shift register are loaded into the M divider and N output
output of the VCO is scaled by a divider prior to being sent divider when S_LOAD transitions from LOW-to-HIGH. The
to each of the LVPECL output buffers. The divider provides M divide and N output divide values are latched on the HIGH-
a 50% output duty cycle.
to-LOW transition of S_LOAD. If S_LOAD is held HIGH, data
at the S_DATA input is passed directly to the M divider and
The programmable features of the ICS8432-11 support two N output divider on each rising edge of S_CLOCK.The serial
input modes to program the PLL M divider and N output mode can be used to program the M and N bits and test bits
divider. The two input operational modes are parallel and T1 and T0.The internal registersT0 and T1 determine the state
serial. Figure1 shows the timing diagram for each mode. In of the TEST output as follows:
parallel mode, the nP_LOAD input is initially LOW. The data
T1 T0
TEST Output
LOW
on inputs M0 through M8 and N0 and N1 is passed directly
to the M divider and N output divider. On the LOW-to-HIGH
transition of the nP_LOAD input, the data is latched and the
M divider remains loaded until the next LOW transition on
0
0
1
1
0
1
0
1
S_Data, Shift Register Input
Output of M divider
CMOS Fout/2
SERIAL
L
OADING
S_CLOCK
T1
T0 *NULL N1
N0
M8
M7
M6
M5
M4 M3
M2
M1
M0
S_DATA
S_LOAD
nP_LOAD
P
ARALLEL LOADING
M0:M8, N0:N1
nP_LOAD
M, N
S_LOAD
Time
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
*NOTE: The NULL timing slot must be observed.
8432CY-11
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REV. E MAY 20, 2005
2
PRELIMINARY
ICS8432-11
Integrated
Circuit
Systems, Inc.
700MHZ/350MHZ, LOW PHASE NOISE,
CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Pullup
Description
1
M5
Input
Input
M divider inputs. Data latched on LOW-to-HIGH transistion of
nP_LOAD input. LVCMOS / LVTTL interface levels.
2, 3, 4,
28, 29,
M6, M7, M8,
M0, M1,
Pulldown
30, 31, 32
M2, M3, M4
Determines N output divider value as defined in Table 3C
Function Table. LVCMOS / LVTTL interface levels.
5, 6
N0, N1
Input
Pulldown
7
nc
Unused
Power
No connect.
8, 16
VEE
Negative supply pins.
Test output which is ACTIVE in the serial mode of operation.
Output driven LOW in parallel mode. LVCMOS interface levels.
9
TEST
VCC
Output
Power
10
Core supply pin.
Half frequency differential output for the synthesizer.
3.3V LVPECL interface levels.
11, 12
13
FOUT/2, nFOUT/2 Output
VCCO
Power
Output
Output supply pin.
Differential output for the synthesizer.
3.3V LVPECL interface levels.
14, 15
FOUT, nFOUT
Active High Master Reset. When logic HIGH, the internal dividers
are rset causing the true outputs (FOUTx) to go low and the
inverted outputs (nFOUTx) to go high. When logic LOW, the
internal dividers and the outputs are enabled. Assertion of MR
does not affect loaded M, N, and T values.
17
MR
Input
Pulldown
LVCMOS / LVTTL interface levels.
Clocks in serial data present at S_DATA input into the shift register
18
19
S_CLOCK
S_DATA
Input
Input
Pulldown on the rising edge of S_CLOCK.
LVCMOS / LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of
Pulldown
S_CLOCK. LVCMOS / LVTTL interface levels.
Controls transition of data from shift register into the dividers.
LVCMOS / LVTTL interface levels.
20
21
S_LOAD
VCCA
Input
Pulldown
Power
Analog supply pin.
Selects between crystal or test inputs as the PLL reference
22
XTAL_SEL
Input
Pullup
source. LVCMOS / LVTTL interface levels. Selects XTAL inputs
when HIGH. Selects TEST_CLK when LOW.
23
TEST_CLK
Input
Input
Pulldown Test clock input. LVCMOS / LVTTL interface levels.
24,
25
XTAL_IN,
XTAL_OUT
Crystal oscillator inputs. XTAL_IN is the input.
XTAL_OUT is the output.
Parallel load input. Determines when data present at M8:M0 is
Pulldown loaded into M divider, and when data present at N1:N0 sets the
N output divider value. LVCMOS / LVTTL interface levels.
26
nP_LOAD
Input
Determines whether synthesizer is in PLL or bypass mode.
LVCMOS / LVTTL interface levels.
27
VCO_SEL
Input
Pullup
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
8432CY-11
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REV. E MAY 20, 2005
3
PRELIMINARY
ICS8432-11
Integrated
Circuit
Systems, Inc.
700MHZ/350MHZ, LOW PHASE NOISE,
CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 3A. PARALLEL AND SERIAL MODES FUNCTION TABLE
Inputs
Conditions
MR nP_LOAD
M
N
S_LOAD S_CLOCK S_DATA
H
X
X
X
X
X
X
Reset. M and N counters reset.
Data on M and N inputs passed directly to the
M divider. TEST output forced LOW.
Data is latched into input registers and remains
loaded until next LOW transition or until a serial
event occurs.
L
L
Data Data
X
X
X
L
↑
Data Data
L
X
X
Serial input mode. Shift register is loaded with
data on S_DATA on each rising edge of
S_CLOCK.
Contents of the shift register are passed to the
M divider.
L
L
H
H
X
X
X
X
L
↑
Data
Data
↑
L
L
L
H
H
X
X
X
X
↓
L
Data
X
M divider and N output divider values are latched.
Parallel or serial input do not affect shift registers.
L
X
S_DATA passed directly to M divider as it is
clocked.
L
H
X
X
H
↑
Data
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓ = Falling edge transition
TABLE 3B. PROGRAMMABLE VCO FREQUENCY FUNCTION TABLE
256
M8
0
128
M7
0
64
M6
0
32
M5
0
16
M4
0
8
M3
1
4
M2
0
2
M1
0
1
M0
0
VCO Frequency
(MHz)
M Divide
200
225
250
275
•
8
9
0
0
0
0
0
1
0
0
1
10
11
•
0
0
0
0
0
1
0
1
0
0
0
0
0
0
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
650
675
700
26
27
28
0
0
0
0
1
1
0
1
0
0
0
0
0
1
1
0
1
1
0
0
0
0
1
1
1
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to crystal or TEST_CLK input frequency of
25MHz.
TABLE 3C. PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Output Frequency (MHz)
Inputs
N Divider Value
FOUT
FOUT/2
N1
0
N0
0
Minimum
200
Maximum
700
Minimum
125
Maximum
350
1
2
4
8
0
1
100
350
62.5
175
1
0
50
175
31.25
15.625
87.5
1
1
25
87.5
43.75
8432CY-11
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REV. E MAY 20, 2005
4
PRELIMINARY
ICS8432-11
Integrated
Circuit
Systems, Inc.
700MHZ/350MHZ, LOW PHASE NOISE,
CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
CC
Inputs, V
-0.5V to VCC + 0.5V
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, IO
Continuous Current
Surge Current
50mA
100mA
PackageThermal Impedance, θ
47.9°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol
VCC
Parameter
Test Conditions
Minimum Typical Maximum Units
Positive Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.135
3.135
3.3
3.3
3.3
3.465
3.465
3.465
110
V
V
VCCA
VCCO
IEE
V
mA
mA
ICCA
15
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
M0-M4, M6-M8, N0, N1, MR,
2
VCC + 0.3
0.8
V
V
-0.3
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
VCC = VIN = 3.465V
150
5
µA
µA
µA
Input
High Current
IIH
M5, XTAL_SEL, VCO_SEL
VCC = VIN = 3.465V
VCC = 3.465V,
M0-M4, M6-M8, N0, N1, MR,
S_CLOCK, TEST_CLK,
S_DATA, S_LOAD, nP_LOAD
-5
V
IN = 0V
Input
Low Current
IIL
VCC = 3.465V,
VIN = 0V
M5, XTAL_SEL, VCO_SEL
TEST; NOTE 1
-150
2.6
µA
V
Output
High Voltage
VOH
VOL
Output
Low Voltage
TEST; NOTE 1
0.5
V
NOTE 1: Outputs terminated with 50Ω to VCCO/2. See “Parameter Measurement Information”section,
“3.3V Output LoadTest Circuit” figure.
8432CY-11
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REV. E MAY 20, 2005
5
PRELIMINARY
ICS8432-11
Integrated
Circuit
Systems, Inc.
700MHZ/350MHZ, LOW PHASE NOISE,
CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
TABLE 4C. LVPECL DC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
VCCO - 1.4
VCCO - 2.0
0.6
Typical
Maximum Units
VOH
Output High Voltage; NOTE 1
VCCO - 0.9
VCCO - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with 50 Ω to VCCO - 2V.
TABLE 5. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
TEST_CLK; NOTE 1
12
25
MHz
MHz
MHz
XTAL_IN, XTAL_OUT;
NOTE 1
fIN
Input Frequency
12
25
S_CLOCK
TBD
NOTE 1: For the input crystal and TEST_CLK frequency range, the M value must be set for the VCO to operate within the
200MHz to 700MHz range. Using the minimum input frequency of 12MHz, valid values of M are 17 ≤ M ≤ 58. Using the
maximum frequency of 25MHz, valid values of M are 8 ≤ M ≤ 28.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
12
25
70
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 7. AC CHARACTERISTICS, VCC = VCCA = VCCO = 3.3V 5%, TA = 0°C TO 70°C
Symbol
FOUT
Parameter
Test Conditions
Minimum Typical Maximum
Units
Output Frequency
25
700
25
MHz
ps
ps
ps
ps
ps
ns
ns
ns
ns
ns
ns
%
tjit(cc)
tjit(per)
tsk(o)
tR
Cycle-to-Cycle Jitter; NOTE 1, 3
Period Jitter, RMS; NOTE 1, 3
Output Skew; NOTE 2, 3
Output Rise Time
TBD
TBD
700
700
20% to 80% @ 50MHz
20% to 80% @ 50MHz
300
300
5
tF
Output Fall Time
M, N to nP_LOAD
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
M, N to nP_LOAD
5
tS
Setup Time
Hold Time
5
5
tH
S_DATA to S_CLOCK
S_CLOCK to S_LOAD
5
5
odc
Output Duty Cycle
PLL Lock Time
47
53
10
tLOCK
ms
All parameters measured at 500MHz unless noted otherwise.
NOTE 1: Jitter performance using XTAL inputs.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
8432CY-11
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REV. E MAY 20, 2005
6
PRELIMINARY
ICS8432-11
Integrated
Circuit
Systems, Inc.
700MHZ/350MHZ, LOW PHASE NOISE,
CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2V
VOH
SCOPE
VCC
VCCA, VCCO
,
Qx
VREF
VOL
LVPECL
1σ contains 68.26% of all measurements
2σ contains 95.4% of all measurements
3σ contains 99.73% of all measurements
4σ contains 99.99366% of all measurements
6σ contains (100-1.973x10-7)% of all measurements
nQx
VEE
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
PERIOD JITTER
nFOUT
FOUT
nFOUT,
nFOUT/2
FOUT,
FOUT/2
➤
➤
nFOUT/2
tcycle n
tcycle n+1
➤
➤
FOUT/2
tsk(o)
tjit(cc) = tcycle n –tcycle n+1
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nFOUT,
nFOUT/2
80%
tF
80%
FOUT,
FOUT/2
tPW
VSWING
20%
Clock
20%
tPERIOD
Outputs
tR
tPW
odc =
x 100%
tPERIOD
OUPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
8432CY-11
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REV. E MAY 20, 2005
7
PRELIMINARY
ICS8432-11
Integrated
Circuit
Systems, Inc.
700MHZ/350MHZ, LOW PHASE NOISE,
CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
APPLICATIONS
STORAGE AREA NETWORKS
A variety of technologies are used for interconnection of the
elements within a SAN. The tables below list the common
application frequencies as well as the ICS8432-11 configu-
rations used to generate the appropriate frequency.
Table 8. COMMON SANS APPLICATIONS FREQUENCIES
Interconnect Technology
Clock Rate
Reference Frequency to SERDES (MHz) Crystal Frequency (MHz)
Gigabit Ethernet
1.25 GHz
125, 250, 156.25
106.25, 53.125, 132.8125
125, 250
25, 19.53125
16.6015625, 25
25
FC1 1.0625 GHz
FC2 2.1250 GHz
Fibre Channel
Infiniband
2.5 GHz
Table 9. CONFIGURATION DETAILS FOR SANS APPLICATIONS
ICS8432-11
ICS8432-11
Interconnect
Technology
Crystal Frequency
(MHz)
Output Frequency
M & N Settings
to SERDES
(MHz)
M8 M7 M6 M5 M4 M3 M2 M1 M0 N1 N0
25
125
250
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
0
0
1
1
1
0
1
1
0
1
1
0
0
1
0
0
0
0
0
0
1
1
0
0
0
0
0
1
1
0
0
0
0
0
0
0
0
0
0
0
1
0
1
1
0
0
0
1
0
1
1
1
1
1
1
0
0
1
0
0
1
0
0
0
1
25
Gigabit Ethernet
25
156.25
156.25
53.125
106.25
132.8125
125
19.53125
25
Fiber Channel 1
Fiber Channel 2
Infiniband
25
16.6015625
25
25
250
8432CY-11
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REV. E MAY 20, 2005
8
PRELIMINARY
ICS8432-11
Integrated
Circuit
Systems, Inc.
700MHZ/350MHZ, LOW PHASE NOISE,
CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS8432-11 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VCC, VCCA, and VCCO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 2. POWER SUPPLY FILTERING
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
50Ω transmission lines. Matched impedance techniques should
be used to maximize operating frequency and minimize signal
distortion. Figures 3A and 3B show two different layouts which
are recommended only as guidelines. Other suitable clock lay-
outs may exist and it would be recommended that the board
designers simulate to guarantee compatibility across all printed
circuit and clock component process variations.
FOUT and nFOUT are low impedance follower outputs that gen-
erate ECL/LVPECL compatible outputs.Therefore, terminating
resistors (DC current path to ground) or current sources must
be used for functionality. These outputs are designed to drive
3.3V
Z
o = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 3A. LVPECL OUTPUT TERMINATION
FIGURE 3B. LVPECL OUTPUT TERMINATION
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LAYOUT GUIDELINE
The schematic of the ICS8432-11 layout example used in this out in the actual system will depend on the selected component
layout guideline is shown in Figure 4A. The ICS8432-11 recom- types, the density of the components, the density of the traces,
mended PCB board layout for this example is shown in Figure and the stacking of the P.C.board.
4B.This layout example is used as a general guideline.The lay-
C1
C2
X1
U1
VCC
1
24
R7
10
M5
M6
M7
M8
N0
N1
nc
X_IN
T_CLK
XTAL_SEL
VCCA
S_LOAD
S_DATA
S_CLOCK
MR
REF_IN
XTAL_SEL
2
3
4
5
6
7
8
23
22
21
20
19
18
17
VCCA
S_LOAD
S_DATA
S_CLOCK
C11
C16
10u
0.01u
VEE
ICS8432-11
VCC
R1
R3
125
125
Zo = 50 Ohm
IN+
C14
0.1u
TL1
+
-
C15
0.1u
Zo = 50 Ohm
IN-
TL2
VCC=3.3V
R2
84
R4
84
FIGURE 4A. SCHEMATIC OF RECOMMENDED LAYOUT
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• The differential 50Ω output traces should have same
length.
The following component footprints are used in this layout
example:
• Avoid sharp angles on the clock trace.Sharp angle
turns cause the characteristic impedance to change on
the transmission lines.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C14 and C15, as close as pos-
sible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
• Keep the clock traces on the same layer.Whenever pos-
sible, avoid placing vias on the clock traces. Placement
of vias on the traces can affect the trace characteristic
impedance and hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a spearation of at least three trace
widths between the differential clock trace and the other
signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors.This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VCCA pin as possible.
• Make sure no other signal traces are routed between the
clock trace pair.
CLOCK TRACES AND TERMINATION
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure.The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location.While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
24 (XTAL_IN) and 25 (XTAL_OUT).The trace length between the
X1 and U1 should be kept to a minimum to avoid unwanted para-
sitic inductance and capacitance. Other signal traces should not
be routed near the crystal traces.
X1
GND
VCC
VIA
U1
PIN 1
C11
C16
VCCA
R7
Close to the input
pins of the
receiver
R4
R3
TL1N
C15
C14
TL1
R2
R1
TL1, TL2 are 50 Ohm traces and
equal length
FIGURE 4B. PCB BOARD LAYOUT FOR ICS8432-11
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POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS8432-11.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS8432-11 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5% = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 110mA = 381.2mW
Power (outputs)MAX = 30mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 381.2mW + 60.4mW = 441.2mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = JunctionTemperature
θ
JA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W perTable 10 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.441W * 42.1°C/W = 88.6°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 10. THERMAL RESISTANCE Θ FOR 32-PIN LQFP, FORCED CONVECTION
JA
θJA byVelocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
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3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in Figure 5.
VCCO
Q1
VOUT
R L
50
VCCO - 2V
FIGURE 5. LVPECL DRIVER CIRCUIT AND TERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CCO
•
•
For logic high, VOUT = V
= V
– 1.0V
OH_MAX
CCO_MAX
)
= 1.0V
OH_MAX
(V
- V
CCO_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CCO_MAX
)
= 1.7V
OL_MAX
(V
- V
CCO_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
- V
/R ] * (V
- V
) =
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
CCO_MAX
OH_MAX
L
L
[(2V - 1V)/50Ω) * 1V = 20.0mW
))
Pd_L = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
/R ] * (V
- V
) =
OL_MAX
CCO_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
[(2V - 1.7V)/50Ω) * 1.7V = 10.2mW L
L
Total Power Dissipation per output pair = Pd_H + Pd_L = 30.2mW
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RELIABILITY INFORMATION
TABLE 11. θJAVS. AIR FLOW TABLE FOR 32 LEAD LQFP
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS8432-11 is: 3765
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PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 12. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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TABLE 13. ORDERING INFORMATION
Part/Order Number
ICS8432CY-11
Marking
Package
Shipping Packaging Temperature
ICS8432CY-11
ICS8432CY-11
32 Lead LQFP
32 Lead LQFP
tray
0°C to 70°C
0°C to 70°C
ICS8430CY-11T
1000 tape & reel
The aforementioned trademark, HiPerClockS™ is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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