ICS84330-03 [ICSI]
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER; 700MHZ ，低抖动，水晶- TO- 3.3V的差分LVPECL频率合成器
| 型号： | ICS84330-03 |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | 700MHZ, LOW JITTER, CRYSTAL-TO-3.3V DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER |
| 文件： | 总20页 (文件大小：248K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
GENERAL DESCRIPTION
FEATURES
• Fully integrated PLL, no external loop filter requirements
• Two differential 3.3V LVPECL output
The ICS84330-03 is a general purpose, dual
ICS
HiPerClockS™
output high frequency synthesizer and a mem-
ber of the HiPerClockS™ family of High Perfor-
mance Clock Solutions from ICS. The VCO
operates at a frequency range of 250MHz to
• Crystal oscillator interface: 10MHz to 25MHz
• Output frequency range: 41.67MHz to 700MHz
• VCO range: 250MHz to 700MHz
700MHz. The VCO and output frequency can be pro-
grammed using the I2C interface. The output can be config- • Parallel or I2C interface for programming M and N dividers
during power-up
ured to divide the VCO frequency by 1, 2, 3, 4, and 6.
• Supports Spread Spectrum Clocking (SSC)
Additionally, the device supports spread spectrum clock-
ing (SSC) for minimizing Electromagnetic Interference
(EMI). The low cycle-cycle jitter and broad frequency
range of the ICS84330-03 make it an ideal clock gen-
erator for a variety of demanding applications which
require high performance.
Center spread: selectable 0.5ꢀ, 1.0ꢀ, 1.5ꢀ, 2ꢀ
Up/Down spread: selectable 0.5ꢀ, 1.0ꢀ, 1.5ꢀ, 2ꢀ,
2.5ꢀ, 3ꢀ, 3.5ꢀ, 4ꢀ
• RMS Period jitter: 9ps (maximum)
• Cycle-to-cycle jitter: 40ps (maximum)
• 3.3V supply voltage
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
• Available in both standard and lead-free RoHS-compliant
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
32 31 30 29 28 27 26 25
Pullup
VCO_SEL
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
SCL
SDA
VCO_SEL
N1
XTAL_IN
OSC
ICS84330-03
32-Lead LQFP
Y package
7mm x 7mm x 1.4mm
body package
Top View
ADDR_SEL
VCCA
N0
1
M8
XTAL_OUT
VCCA
M7
Pulldown
FREF_EXT
XTAL_SEL
0
FREF_EXT
XTAL_SEL
M6
M5
÷16
M4
Pullup
XTAL_IN
9
10 11 12 13 14 15 16
PLL
VCO
Phase Detector
0
1
÷1
÷2
1
0
Q0
÷M
÷2
nQ0
÷2
÷3
1
0
Q1
nQ1
÷4
÷6
Pulldown
ADDR_SEL
SDA
I2C Parallel Interface
SCL
Pullup
nP_LOAD
M0:M7 = Pulldown, M8 = Pullup
M0:M8
Pulldown
Pulldown
N0
N1
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REV.A FEBRUARY 2, 2006
1
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
The ICS84330-03 uses either a parallel interface or indus- The programming mode is controlled by the nP_LOAD pin.
try standard I2C interface to control the programming of the When this pin is low, The M, N values are set by the logic
internal dividers. The power on defaults are summarized as values on the M, N pins. If nP_LOAD is HIGH, the M, N
follows:
dividers can be changed using the I2C serial programming
interface.
M
Output
Q0/nQ0 output at 267MHz
The I2C control registers are defined below:
Parallel Mode: 256
(using a 16.667MHz crystal)
Q1/nQ1 output at 133MHz
(using a 16.667MHz crystal)
SSC Mode:
Off
Data Byte 0
Control Bit
N1
0
N0
0
M8
1
M7
0
M6
0
M5
0
M4
0
M3
0
Power-up Default Value
Data Byte 1
Control Bit
Not
Used
Not
Used
Not
Used
Not
Used
Not
Used
M2
0
M1
0
M0
0
Power-up Default Value
X
X
X
X
X
Data Byte 2
Control Bit
Up
0
Down SSC5 SSC4 SSC3 SSC2 SSC1 SSC0
Power-up Default Value
0
0
0
0
0
0
0
I2C ADDRESSING
The ICS84330-03 can be set to decode one of two addresses
to minimize the chance of address conflict on the I2C bus.The
address that is decoded is controlled by the setting of the
ADDR_SEL pin (pin 3).
ADDR_SEL (pin 3) = 0 Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
1
1
0
0
R/W
ADDR_SEL (pin 3) = 1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
1
1
0
1
1
1
0
R/W
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REV.A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
I2C INTERFACE - PROTOCOL
The ICS84330-03 is a slave-only device and uses the stan- mum SCL frequency is greater than 10MHz which is more
dard I2C protocol as shown in the below diagrams. The maxi- than sufficient for standard I2C clock speeds.
SCL
SDA
START
Valid Data
Acknowledge
STOP
START (ST) – defined as high-to-low transition on SDA while holding SCL HIGH.
DATA - Between START and STOP cycles, SDA is synchronous with SCL.
Data may change only when SCL is LOW and must be stable when SCL is HIGH.
ACKNOWLEDGE (AK) – SDA is driven LOW before the SCL rising edge and
held LOW until the SCL falling edge.
STOP (SP) – defined as low-to-high transition on SDA while holding SCL HIGH.
I2C INTERFACE - AWRITE EXAMPLE
A serial transfer to the ICS84330-03 always consists of an and the master generates a stop condition, the values in the
address cycle followed by 4 data bytes: 1 dummy byte fol- serial control register are latched into the M divider, N divider,
lowed by 3 data bytes. Any additional bytes beyond the 4 data and control bits and the device will smoothly slew to the new
bytes will not be acknowledged and the ICS84330-03 will frequency and any changes to the state of the control bits will
leave the data bus HIGH. These extra bits will not be loaded take effect.
into the serial control register.Once the 4 Data bytes are loaded
ST
Slave Address: 7 Bits
R/W
AK
1 Bit Refer to page 2 for address choices based on ADDR_SEL pin setting
1 Bit
1 Bit
Dummy Byte 0: 8 Bits
AK
1 Bit
Data Byte 0: 8 Bits
AK
N1
M2
N0
M8
M7
M6
M5
M4
M3
1 Bit
Data Byte 1: 8 Bits
Not
Used
AK
Not
Used
Not
Used
Not
Used
Not
Used
M1
M0
1 Bit
Data Byte 2: 8 Bits
SSC4 SSC3
AK
SP
1 Bit
↑
Up
Down
SSC5
SSC2
SSC1
SSC0
1 Bit
Data Byte values latched into control registers here.
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REV.A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
SPREAD SPECTRUM OPERATION
NOTE: The functional description that follows used a has been selected and the M-divider value will toggle be-
16.6667MHz crystal with an M divide value of 160.
tween the programmed M value, and M-SS at a 32kHz rate.
When both the UP and DN bits are HIGH, then center-
Spread Spectrum operation is controlled by I2C Data Byte spread has been selected and the M-divider will toggle
2, Spread Spectrum Control Register. Bits SSC0 – SSC5 between M+SS and M-SS at a 32kHz rate. The table below
(SS) of the register are a subtrahend to the M-divider for shows the desired SS value to achieve 0.5ꢀ, 1ꢀ and 1.5ꢀ
down-spread, and they are an addend and a subtrahend to spread at selected VCO frequencies. To disable Spread
the M-divider for center-spread. When the UP bit is HIGH, Spectrum operation, program both the UP and DN bits to
then up-spread has been selected and the M-divider value LOW. Spread Spectrum operation will also be disabled when
will toggle between the programmed M value, and M+SS at the nP_LOAD input is LOW.
a 32kHz rate. When the DN bit is HIGH, then down-spread
TABLE 1A. SS MODE FUNCTIONT ABLE
Register Bits
SSC7
SSC6
SS Mode
0
0
Off
0
1
1
1
0
1
Down-Spread
Up-Spread
Center-Spread
TABLE 1B. UP/DOWN SPREAD CONFIGURATION
Up- or Down-Spread SS Value
SSC5
SSC4
SSC3
SSC2
SSC1
SSC0
Spread %
0
0
0
0
0
1
0.50
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
1
1
1
1
0
1
1
0
0
1
1
0
0
1
0
1
0
1
0
0
0
0
0
0
0
0
1.00
1.50
2.00
2.50
3.00
3.50
4.00
TABLE 1C. CENTER SPREAD CONFIGURATION
Center-Spread SS Value
SSC5
SSC4
SSC3
SSC2
SSC1
SSC0
Spread ( ) %
0
0
0
0
0
1
0.50
0
0
0
0
0
0
0
0
1
1
1
0
0
1
0
0
0
0
1.00
1.50
2.00
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REV.A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
FUNCTIONAL DESCRIPTION
The programmable features of the ICS84330-03 support
two input modes to program the M divider and N output
divider. The two input operational modes are parallel and
I2C. Figure 1 shows the timing diagram for parallel mode. In
parallel mode the nP_LOAD input is LOW. The data on
inputs M0 through M8 and N0 through N1 is passed
directly to the M divider and N output divider. On the LOW-
to-HIGH transition of the nP_LOAD input, the data is latched
and the M divider remains loaded until the next LOW tran-
sition on nP_LOAD or until an I2C event occurs. The rela-
tionship between the VCO frequency, the crystal frequency
NOTE: The functional description that follows describes op-
eration using a 16.6667MHz crystal. Valid PLL loop divider
values for different crystal or input frequencies are defined
in the Input Frequency Characteristics, Table 7, NOTE 1.
The ICS84330-03 features a fully integrated PLL and
therefore requires no external components for setting the
loop bandwidth. A quartz crystal is used as the input to the
on-chip oscillator. The output of the oscillator is divided by
16 prior to the phase detector.
fxtal
16
and the M divider is defined as follows:
The phase detector and the M divider force the VCO output
frequency to be 2M times the reference frequency by
adjusting the VCO control voltage. Note that for some
values of M (either too high or too low), the PLL will not
achieve lock. The output of the VCO is scaled by a divider
prior to being sent to each of the LVPECL output buffers.
The divider provides a 50ꢀ output duty cycle.
x
fVCO =
2M
The M value and the required values of M0 through M8 are
shown in Table 3B, Programmable VCO Frequency Func-
tion Table. Valid M values for which the PLL will achieve
lock are defined as 120 ≤ M ≤ 336. The frequency out is
fVCO fxtal 2M
defined as follows:
fout
x
=
=
N
N
16
PARALLEL
LOADING
M, N
M0:M8, N0:N1
nP_LOAD
Time
FIGURE 1. PARALLEL LOAD OPERATIONS
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REV.A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 2. PIN DESCRIPTIONS
Number
Name
SCL
Type
Description
1
2
Input
Input
Input
Power
Input
NOTE 1 I2C serial clock input.
NOTE 1 I2C serial data input.
SDA
3
ADDR_SEL
VCCA
Pulldown Serial address select pin. LVCMOS / LVTTL interface levels.
Analog supply pin.
4, 5
6
FREF_EXT
Pulldown PLL reference input. LVCMOS / LVTTL interface levels.
Selects between the crystal oscillator or FREF_EXT inputs as the PLL
7
XTAL_SEL
Input
Pullup
reference source. Selects XTAL inputs when HIGH. Selects FREF_EXT
when LOW. LVCMOS / LVTTL interface levels.
XTAL_IN,
XTAL_OUT
Crystal oscillator interface. XTAL_IN is an oscillator input.
XTAL_OUT is an oscillator output.
8, 9
10
Input
Input
OE
Pullup
Pullup
Output enable. LVCMOS / LVTTL interface levels.
Parallel load input. Determines when data present at M8:M0 is loaded
into M divider, and when data present at N1:N0 sets the N output divide
value. LVCMOS / LVTTL interface levels.
11
nP_LOAD
Input
Input
12, 13, 14, M0, M1, M2
15, 17, 18, M3, M4, M5
Pulldown
Pullup
M divider inputs. Data latched on LOW-to-HIGH transition of nP_LOAD
input. LVCMOS / LVTTL interface levels.
19, 20
21
M6, M7
M8
Input
16
nc
Unused
No connect.
Determines N output divider value as defined in Table 4B Function
Table. LVCMOS / LVTTL interface levels.
When logic LOW, bypass PLL. When logic HIGH, PLL is active.
LVCMOS/LVTTL interface levels.
22, 23
24
N0, N1
Input
Input
Pulldown
Pullup
VCO_SEL
25, 29
26, 32
27, 28
30, 31
VEE
Power
Power
Output
Output
Negative supply pins.
VCC
Core supply pins.
nQ1, Q1
nQ0, Q0
Differential clock outputs. LVPECL interface levels.
Differential clock outputs. LVPECL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 3, Pin Characteristics, for typical values.
NOTE 1: Pullup resistor is only active in parallel mode.
TABLE 3. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
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REV.A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 4A. PROGRAMMABLEVCO FREQUENCY FUNCTIONT ABLE
256
M8
0
128
M7
0
64
M6
1
32
M5
1
16
M4
1
8
M3
1
4
M2
0
2
M1
0
1
M0
0
VCO Frequency
(MHz)
M Divide
250
252
254
256
•
120
121
122
123
•
0
0
1
1
1
1
0
0
1
0
0
1
1
1
1
0
1
0
0
0
1
1
1
1
0
1
1
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
•
696
698
700
334
335
336
1
0
1
0
0
1
1
1
0
1
0
1
0
0
1
1
1
1
1
0
1
0
1
0
0
0
0
NOTE 1: These M divide values and the resulting frequencies correspond to a crystal frequency of 16.6667MHz.
TABLE 4B. PROGRAMMABLE OUTPUT DIVIDER FUNCTIONTABLE
Inputs
Outputs
N1
0
N0
0
Q0/nQ0
÷2
Q1/nQ1
÷4
0
1
÷1
÷2
1
0
÷2
÷6
1
1
÷1
÷3
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REV.A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.±V to VCC + 0.± V
I
Outputs, IO
Continuous Current
Surge Current
±0mA
100mA
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, T -6±°C to 1±0°C
STG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VCC = VCCA = 3.3V±±5, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.13±
Typical
3.3
Maximum Units
VCC
VCCA
ICC
Core Supply Voltage
3.46±
3.46±
180
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.13±
3.3
V
mA
mA
ICCA
1±
TABLE 5B. LVCMOS / LVTTL DC CHARACTERISTICS, VCC = VCCA = 3.3V±±5, TA = 0°C TO 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
M8, N0, N1, OE,
2
VCC + 0.3
0.8
V
V
-0.3
V
CC = VIN = 3.46±V
±
µA
µA
µA
µA
nP_LOAD, XTAL_SEL
ADDR_SEL, SDA,
SCL, FREF_EXT,
VCO_SEL, M0:M7
M8, N0, N1, OE,
Input
High Current
IIH
VCC = VIN = 3.46±V
1±0
VCC = 3.46±V, VIN = 0V
VCC = 3.46±V, VIN = 0V
-1±0
-±
nP_LOAD, XTAL_SEL
ADDR_SEL, SDA,
SCL, FREF_EXT,
VCO_SEL, M0:M7
Input
Low Current
IIL
TABLE 5C. LVPECL DC CHARACTERISTICS, VCC =VCCA = 3.3V±±5, TA = 0°C TO 70°C
Symbol Parameter Test Conditions
Minimum
VCC - 1.4
VCC - 2.0
0.6
Typical Maximum Units
VOH
Output High Voltage; NOTE 1
VCC - 0.9
VCC - 1.7
1.0
V
V
V
VOL
Output Low Voltage; NOTE 1
VSWING
Peak-to-Peak Output Voltage Swing
NOTE 1: Outputs terminated with ±0Ω to VCC - 2V.
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REV.A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
10
25
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 7. INPUT FREQUENCY CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
fIN
Test Conditions
Minimum Typical Maximum Units
XTAL; NOTE 1
10
25
10
MHz
MHz
MHz
Input Frequency SCL
FREF_EXT; NOTE 2
10
NOTE 1: For the crystal frequency range the M value must be set to achieve the minimum or maximum VCO frequency
range of 250MHz to 700MHz. Using the minimum frequency of 10MHz, valid values of M are 200 ≤ M ≤ 511.
Using the maximum frequency of 25MHz, valid values of M are 80 ≤ M ≤ 224.
NOTE 2: Maximum frequency on FREF_EXT is dependent on the internal M counter limitations. See Application
Information Section for recommendations on optimizing the performance using the FREF_EXT input.
TABLE 8. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum
Units
MHz
ps
FOUT
Output Frequency
700
9
tjit(per)
tjit(cc)
tsk(o)
tR / tF
Period Jitter, RMS; NOTE 1, 2
Cycle-to-Cycle Jitter; NOTE 1, 2
Output Skew; NOTE 3
3
20
40
ps
80
900
ps
Output Rise/Fall Time
20ꢀ to 80ꢀ
200
20
ps
SDA to SCL
Setup Time
ns
tS
M, N to nP_LOAD
20
ns
SDA to SCL
Hold Time
20
ns
tH
M, N to nP_LOAD
20
ns
SSC Modulation Frequency;
NOTE 4
FM
XTAL_IN = 16.6667MHz
30
-7
32
33.33
kHz
SSCred
tL
Spectral Reduction; NOTE 4
PLL Lock Time
-10
dB
ms
ꢀ
10
52
odc
tPW
Output Duty Cycle
N ≠ ÷1
48
Output Pulse Width
N = ÷1
tPERIOD/2 - 275 tPERIOD/2 tPERIOD/2 + 275
ps
See Parameter Measurement Information section.
Characterized using a XTAL input.
NOTE 1: This parameter is defined in accordance with JEDEC Standard 65
NOTE 2: See Applications section.
NOTE 3: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured from the output differential cross points.
NOTE 4: Spread Spectrum clocking enabled.
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REV.A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PARAMETER MEASUREMENT INFORMATION
2V
2V
VOH
VREF
SCOPE
VCC
Qx
VCCA
VOL
1σ contains 68.26ꢀ of all measurements
2σ contains 95.4ꢀ of all measurements
LVPECL
3σ contains 99.73ꢀ of all measurements
4σ contains 99.99366ꢀ of all measurements
6σ contains (100-1.973x10-7)ꢀ of all measurements
nQx
VEE
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
-1.3V 0.165V
3.3V OUTPUT LOAD AC TEST CIRCUIT
PERIOD JITTER
nQ0, nQ1
Q0, Q1
nQx
Qx
➤
➤
tcycle n+1
tcycle n
➤
➤
nQy
Qy
tjit(cc) = tcycle n –tcycle n+1
tsk(o)
1000 Cycles
CYCLE-TO-CYCLE JITTER
OUTPUT SKEW
nQ0, nQ1
80ꢀ
80ꢀ
Q0, Q1
VSWING
tPW
Clock
20ꢀ
20ꢀ
tPERIOD
Outputs
tF
tR
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALL TIME
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REV.A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS84330-03 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VCC and VCCA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VCCA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V
VCC
.01μF
.01μF
10Ω
VCCA
10μF
FIGURE 2. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
OUTPUTS:
LVPECL OUTPUT
INPUTS:
SELECT PINS:
All unused LVPECL outputs can be left floating. We
recommend that there is no trace attached. Both sides of the
differential output pair should either be left floating or
terminated.
All select pins have internal pull-ups and pull-downs;
additional resistance is not required but can be added for
additional protection. A 1kΩ resistor can be used.
CRYSTAL INPUT INTERFACE
The ICS84330-03 has been characterized with 18pF paral- parallel resonant crystal over the frequency range and other
lel resonant crystals. The capacitor values, C1 and C2, parameters specified in this data sheet. The optimum C1
shown in Figure 3 below were determined using an 18pF and C2 values can be slightly adjusted for different board
parallel resonant crystal and were chosen to minimize the layouts.
ppm error. These same capacitor values will tune any 18pF
XTAL_IN
C1
22p
X1
18pF Parallel Cry stal
XTAL_OUT
C2
22p
Figure 3.CRYSTAL INPUt INTERFACE
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
LVCMOS TO XTAL INTERFACE
The XTAL_IN input can accept a single-ended LVCMOS impedance of the driver (Ro) plus the series resistance
(Rs) equals the transmission line impedance. In addition,
signal through an AC couple capacitor. A general interface
diagram is shown in Figure 4. The XTAL_OUT pin can matched termination at the crystal input will attenuate the
be left floating. The input edge rate can be as slow as signal in half. This can be done in one of two ways. First,
R1 and R2 in parallel should equal the transmission line
10ns. For LVCMOS inputs, it is recommended that the
amplitude be reduced from full swing to half swing in order impedance. For most 50Ω applications, R1 and R2 can be
to prevent signal interference with the power rail and to 100Ω. This can also be accomplished by removing R1 and
making R2 50Ω.
reduce noise. This configuration requires that the output
VDD
VDD
R1
.1uf
Ro
Rs
Zo = 50
XTAL_IN
R2
Zo = Ro + Rs
XTAL_OU T
Figure 4. GENERAL DIAGRAM FOR LVCMOS DRIVER TO XTAL INPUT INTERFACE
50
40
30
20
10
0
Spec Limit
N = 1
200
300
400
500
600
700
Output Frequency (MHz)
FIGURE 5. CYCLE-TO-CYCLE JITTER VS. fOUT (using a 16MHz XTAL)
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
JITTER REDUCTION FOR FREF_EXT SINGLE END INPUT
If the FREF_EXT input is driven by a 3.3V LVCMOS driver, the
jitter performance can be improved by reducing the amplitude
swing and slowing down the edge rate. Figure 6A shows an
amplitude reduction approach for a long trace. The swing will
be approximately 0.85V for logic low and 2.5V for logic high
(instead of 0V to 3.3V). Figure 6B shows amplitude reduction
approach for a short trace. The circuit shown in Figure 6C
reduces amplitude swing and also slows down the edge rate
by increasing the resistor value.
VDD
R1
VDD
100
Zo = 50 Ohm
Td
Ro ~ 7 Ohm
VDD
GND
RS
43
R2
100
FREF_EXT
Driver_LVCMOS
FIGURE 6A. AMPLITUDE REDUCTION FOR A LONGT RACE
VDD
VDD
R1
200
Ro ~ 7 Ohm
VDD
GND
RS
100
R2
200
FREF_EXT
Driver_LVCMOS
FIGURE 6B. AMPLITUDE REDUCTION FOR A SHORTT RACE
VDD
VDD
R1
400
Ro ~ 7 Ohm
VDD
GND
RS
200
R2
400
FREF_EXT
Driver_LVCMOS
FIGURE 6C. EDGE RATE REDUCTION BY INCREASING THE RESISTOR VALUE
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REV.A FEBRUARY 2, 2006
13
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
SPREAD SPECTRUM
Spread-spectrum clocking is a frequency modulation tech- It is important to note the ICS84330-03 7dB minimum
nique for EMI reduction. When spread-spectrum is enabled, spectral reduction is the component-specific EMI reduc-
a 32kHz triangle waveform is used from the nominal 333MHz tion, and will not necessarily be the same as the system
clock frequency. An example of a triangle frequency modu- EMI reduction.
lation profile is shown in Figure 7A below. The ramp profile
can be expressed as:
• Fnom = Nominal Clock Frequency in Spread OFF mode
(333MHz with 16.6667MHz IN)
• Fm = Nominal Modulation Frequency (32kHz)
• δ = Modulation Factor (0.25ꢀ down spread)
1
(1 - δ) fnom + 2 fm x δ x fnom x t when 0 < t <
,
2 fm
1
1
fm
(1 - δ) fnom - 2 fm x δ x fnom x t when
< t <
2 fm
Δ − 10 dBm
Fnom
B
A
➤
(1 - δ) Fnom
δ = 0.25ꢀ
➤
➤
0.5/fm
1/fm
FIGURE 7A. TRIANGLE FREQUENCY MODULATION
FIGURE 7B. 333MHZ CLOCK OUTPUT IN FREQUENCY DOMAIN
(A) SPREAD-SPECTRUM OFF
(B) SPREAD-SPECTRUM ON
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REV.A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TERMINATION FOR LVPECL OUTPUTS
The clock layout topology shown below is a typical termina-
tion for LVPECL outputs.The two different layouts mentioned
are recommended only as guidelines.
designed to drive 50Ω transmission lines. Matched imped-
ance techniques should be used to maximize operating
frequency and minimize signal distortion. Figures 8A and
8B show two different layouts which are recommended only
as guidelines. Other suitable clock layouts may exist and it
would be recommended that the board designers simulate
to guarantee compatibility across all printed circuit and clock
component process variations.
FOUT and nFOUT are low impedance follower outputs that
generate ECL/LVPECL compatible outputs. Therefore, ter-
minating resistors (DC current path to ground) or current
sources must be used for functionality. These outputs are
3.3V
Zo = 50Ω
125Ω
125Ω
FOUT
FIN
Zo = 50Ω
Zo = 50Ω
Zo = 50Ω
FOUT
FIN
50Ω
50Ω
VCC - 2V
1
RTT =
Zo
RTT
((VOH + VOL) / (VCC – 2)) – 2
84Ω
84Ω
FIGURE 8A. LVPECL OUTPUTTERMINATION
FIGURE 8B. LVPECL OUTPUTT ERMINATION
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REV.A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS84330-03.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS84330-03 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VCC = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
NOTE: Please refer to Section 3 for details on calculating power dissipated in the load.
•
•
Power (core)MAX = VCC_MAX * IEE_MAX = 3.465V * 180mA = 623.7mW
Power (outputs)MAX = 30.2mW/Loaded Output pair
If all outputs are loaded, the total power is 2 * 30mW = 60mW
Total Power_MAX (3.465V, with all outputs switching) = 623.7 + 60mW = 683.7mW
2. JunctionTemperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of the
device.The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-AmbientThermal Resistance
Pd_total =Total Device Power Dissipation (example calculation is in section 1 above)
TA = AmbientTemperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used. Assuming a
moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per Table 9 below.
Therefore, Tj for an ambient temperature of 70°C with all outputs switching is:
70°C + 0.684W * 42.1°C/W = 98.8°C. This is well below the limit of 125°C.
This calculation is only an example.Tj will obviously vary depending on the number of loaded outputs, supply voltage, air flow,
and the type of board (single layer or multi-layer).
TABLE 9. THERMAL RESISTANCE θJA FOR 32-PIN LQFP, FORCED CONVECTION
θ
JA by Velocity (Linear Feet per Minute)
0
200
500
Single-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
55.9°C/W
50.1°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
47.9°C/W
42.1°C/W
39.4°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
3. Calculations and Equations.
The purpose of this section is to derive the power dissipated into the load.
LVPECL output driver circuit and termination are shown in the Figure 9.
VCC
Q1
VOUT
RL
50
VCC - 2V
FIGURE 9. LVPECL DRIVER CIRCUIT ANDTERMINATION
To calculate worst case power dissipation into the load, use the following equations which assume a 50Ω load, and a termination
voltage ofV - 2V.
CC
•
•
For logic high, V = V
= V
– 0.9V
OUT
OH_MAX
CC_MAX
)
= 0.9V
OH_MAX
(V
- V
CC_MAX
For logic low, VOUT = V
= V
– 1.7V
OL_MAX
CC_MAX
)
= 1.7V
OL_MAX
(V
- V
CC_MAX
Pd_H is power dissipation when the output drives high.
Pd_L is the power dissipation when the output drives low.
))
Pd_H = [(V
– (V
- 2V))/R ] * (V
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OH_MAX
CC_MAX
CC_MAX
OH_MAX
_MAX
OH_MAX
CC_MAX
OH_MAX
L
CC
L
[(2V - 0.9V)/50Ω] * 0.9V = 19.8mW
Pd_L = [(V – (V - 2V))/R ] * (V
))
- V
) = [(2V - (V
- V
/R ] * (V
- V
) =
OL_MAX
CC_MAX
CC_MAX
OL_MAX
_MAX
OL_MAX
CC_MAX
OL_MAX
L
CC
L
[(2V - 1.7V)/50Ω] * 1.7V = 10.2mW
Total Power Dissipation per output pair = Pd_H + Pd_L = 30mW
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
RELIABILITY INFORMATION
TABLE 10. θJAVS. AIR FLOW 32 LEAD LQFPTABLE
θJA byVelocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84330-03 is: 9304
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REV.A FEBRUARY 2, 2006
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ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
PACKAGE OUTLINE - Y SUFFIX FOR 32 LEAD LQFP
TABLE 11. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
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REV.A FEBRUARY 2, 2006
19
ICS84330-03
700MHZ, LOW JITTER, CRYSTAL-TO-3.3V
DIFFERENTIAL LVPECL FREQUENCY SYNTHESIZER
Integrated
Circuit
Systems, Inc.
TABLE 12. ORDERING INFORMATION
Part/Order Number
ICS84330AY-03
Marking
Package
Shipping Packaging
Tray
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS84330AY03
ICS84330AY03
ICS84330A03L
ICS84330A03L
32 Lead LQFP
ICS84330AY-03T
ICS84330AY-03LF
ICS84330AY-03LFT
32 Lead LQFP
1000 Tape & Reel
Tray
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP
1000 Tape & Reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
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