ICS844003I [ICSI]
FEMTOCLOCKS? CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER; FEMTOCLOCKS ™ CRYSTAL - TO- LVDS频率合成器
| 型号： | ICS844003I |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER |
| 文件： | 总13页 (文件大小：192K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS844003I is a 3 differential output LVDS
• Three LVDS outputs on two banks, A Bank with one LVDS
pair and B Bank with 2 LVDS output pairs
ICS
HiPerClockS™
Synthesizer designed to generate Ethernet refer-
ence clock frequencies and is a member of the
HiPerClocks™family of high performance clock
solutions from ICS. Using a 31.25MHz or
• Using a 31.25MHz or 26.041666MHz crystal, the two
output banks can be independently set for 625MHz,
312.5MHz, 156.25MHz or 125MHz
26.041666MHz, 18pF parallel resonant crystal, the following
frequencies can be generated based on the settings of 4 fre-
quency select pins (DIV_SEL[A1:A0], DIV_SEL[B1:B0]):
625MHz, 312.5MHz, 156.25MHz, and 125MHz. The 844003I
has 2 output banks, Bank A with 1 differential LVDS output
pair and Bank B with 2 differential LVDS output pairs.
• Selectable crystal oscillator interface or LVCMOS/LVTTL
single-ended input
• VCO range: 560MHz to 700MHz
• RMS phase jitter @ 156.25MHz (1.875MHz - 20MHz):
0.63ps (typical)
The two banks have their own dedicated frequency se- • 3.3V output supply mode
lect pins and can be independently set for the frequen-
• -40°C to 85°C ambient operating temperature
cies mentioned above. The ICS844003I uses ICS’ 3rd gen-
eration low phase noise VCO technology and can achieve
1ps or lower typical rms phase jitter, easily meeting
Ethernet jitter requirements. The ICS844003I is packaged
in a small 24-pin TSSOP package.
• Available in both standard and lead-free RoHS-compliant
packages
PIN ASSIGNMENT
1
2
3
DIV_SELB0
VCO_SEL
MR
24
23
22
DIV_SELB1
VDDO_B
QB0
4
5
6
7
VDDO_A
nQB0
21
20
19
18
17
16
15
14
13
QA0
nQA0
CLK_ENB
CLK_ENA
FB_DIV
QB1
nQB1
XTAL_SEL
TEST_CLK
XTAL_IN
XTAL_OUT
GND
8
9
10
11
12
VDDA
VDD
DIV_SELA1
DIV_SELA0
ICS844003I
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
package body
BLOCK DIAGRAM
Pullup
CLK_ENA
DIV_SELA[1:0]
G Package
Pullup
VCO_SEL
TopView
QA0
0 0 ÷1
nQA0
Pulldown
0 1 ÷2 (default)
1 0 ÷4
TEST_CLK
XTAL_IN
0
1
0
1
1 1 ÷5
Phase
Detector
VCO
560-700MHz
OSC
XTAL_OUT
XTAL_SEL
QB0
Pullup
FB_DIV
0 0 ÷1
nQB0
0 1 ÷2
0 = ÷20 (default)
1 = ÷24
1 0 ÷4 (default)
1 1 ÷5
QB1
Pulldown
FB_DIV
DIV_SELB[1:0]
MR
nQB1
Pulldown
Pullup
CLK_ENB
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844003AGI
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REV.B AUGUST 25, 2005
1
PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
DIV_SELB0
DIV_SELB1
Type
Pulldown
Description
Division select pin for Bank B. Default = Low.
LVCMOS/LVTTL interface levels.
VCO select pin. When Low, the PLL is bypassed and the crystal reference
or TEST_CLK (depending on XTAL_SEL setting) are passed directly to the
output dividers. Has an internal pullup resistor so the PLL is not bypassed
by default. LVCMOS/LVTTL interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
1
24
Input
Input
2
3
VCO_SEL
Pullup
MR
Input
Pulldown to go high. When logic LOW, the internal dividers and the outputs are
enabled. Has an internal pulldown resistor so the power-up default state of
outputs and dividers are enabled. LVCMOS/LVTTL interface levels.
4
VDDO_A
Power
Ouput
Output supply pin for Bank A outputs.
5, 6
QA0, nQA0
Differential output pair. LVDS interface levels.
Output enable Bank B. Active High outputs are enable. When logic HIGH,
the output pairs on Bank B are enabled. When logic LOW, the output pairs
are in a high impedance state. Has an internal pullup resistor so the default
7
CLK_ENB
Input
Pullup
power-up state of outputs are enabled. LVCMOS/LVTTL interface levels.
Output enable Bank A. Active High output enable. When logic HIGH,
the output pair in Bank A is enabled. When logic LOW, the output pair is in
Pullup
8
9
CLK_ENA
FB_DIV
Input
Input
a high impedance state. Has an internal pullup resistor so the default
power-up state of output is enabled. LVCMOS/LVTTL interface levels.
Feedback divide select. When Low (default), the feedback divider is set
Pulldown for ÷20. When HIGH, the feedback divider is set for ÷24.
LVCMOS/LVTTL interface levels.
10
11
VDDA
VDD
Power
Power
Analog supply pin.
Core supply pin.
12
13
DIV_SELA0
DIV_SELA1
Division select pin for Bank A. Default = HIGH.
Pullup
Input
LVCMOS/LVTTL interface levels.
14
GND
Power
Power supply ground.
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input. XTAL_IN is also the overdrive pin if you want to overdrive the crystal
circuit with a single-ended reference clock.
XTAL_OUT,
XTAL_IN
15, 16
Input
Input
Input
Single-ended reference clock input. Has an internal pulldown resistor to
Pulldown pull to low state by default. Can leave floating if using the crystal interface.
LVCMOS/LVTTL interface levels.
17
18
TEST_CLK
XTAL_SEL
Crystal select pin. Selects between the single-ended TEST_CLK or crystal
interface. Has an internal pullup resistor so the crystal interface is selected
by default. LVCMOS/LVTTL interface levels.
Pullup
19, 20
21, 22
23
nQB1, QB1 Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Output supply pin for Bank B outputs.
nQB0, QB0
VDDO_B
Output
Power
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
51
51
RPULLUP
Input Pullup Resistor
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REV.B AUGUST 25, 2005
2
PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 3A. BANK A FREQUENCY TABLE
QA0/nQA0
M/N
Multiplication
Factor
Inputs
Feedback
Divider
Bank A
Output Divider
Output
Frequency
(MHz)
Crystal Frequency
DIV_SELA1 DIV_SELA0 FB_DIV
(MHz)
31.25
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
20
20
20
20
24
24
24
24
1
2
4
5
1
2
4
5
20
10
5
625
312.5
156.25
125
31.25
31.25
31.25
4
26.041666
26.041666
26.041666
26.041666
24
12
6
625
312.5
156.25
125
64.8
TABLE 3B. BANK B FREQUENCY TABLE
QB0/nQB0
Output
Frequency
(MHz)
Inputs
M/N
Multiplication
Factor
Feedback
Divider
Bank B
Output Divider
Crystal Frequency
DIV_SELB1 DIV_SELB0 FB_DIV
(MHz)
31.25
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
0
0
0
1
1
1
1
20
20
20
20
24
24
24
24
1
2
4
5
1
2
4
5
20
10
5
625
312.5
156.25
125
31.25
31.25
31.25
4
26.041666
26.041666
26.041666
26.041666
24
12
6
625
312.5
156.25
125
4.8
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3
PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 3C. OUTPUT BANK CONFIGURATION SELECT FUNCTION TABLE
Inputs
DIV_SELB1 DIV_SELB0
Outputs
Inputs
Outputs
QA
÷1
QB
÷1
÷2
÷4
÷5
DIV_SELA1
DIV_SELA0
0
0
1
1
0
1
0
1
0
0
1
1
0
1
0
1
÷2
÷4
÷5
TABLE 3D. FEEDBACK DIVIDER CONFIGURATION SELECT FUNCTION TABLE
Inputs
FB_DIV
Feedback Divide
0
1
÷20
÷24
Enabled
Disabled
TEST_CLK
CLK_ENx
nQA0,
nQB0:nQB1
QA0,
QB0:QB1
FIGURE 1. CLK_EN TIMING DIAGRAM
TABLE 3E. CLK_ENA SELECT FUNCTION TABLE
TABLE 3F. CLK_ENB SELECT FUNCTION TABLE
Inputs
Outputs
Inputs
Outputs
CLK_ENA
QA0
LOW
Active
nQA0
HIGH
Active
CLK_ENB
QB0:QB1
nQB0:nQB1
HIGH
0
1
0
1
LOW
Active
Active
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PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
PackageThermal Impedance, θ
70°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
VDD
Core Supply Voltage
Analog Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
99
3.465
3.465
3.465
V
V
VDDA
VDDO_A, B Output Supply Voltage
V
IDD
Power Supply Current
Analog Supply Current
Output Supply Current
mA
mA
mA
IDDA
10
IDDO_A, B
52
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VDD = 3.3V
2
VDD + 0.3
VDD + 0.3
0.8
V
V
V
V
VIH
VIL
Input High Voltage
Input Low Voltage
TEST_CLK, MR, FB_DIV
V
DD = 2.5V
VDD = 3.3V
DD = 2.5V
1.7
-0.3
-0.3
V
0.7
VDD = VIN = 3.465V
or 2.625V
150
µA
µA
µA
µA
DIV_SELA1, DIV_SELB0
Input
High Current
IIH
DIV_SELB1, DIV_SELA0,
VCO_SEL, XTAL_SEL,
CLK_ENA, CLK_ENB
VDD = VIN = 3.465V
or 2.625V
5
VDD = 3.465V or 2.625V,
TEST_CLK, MR, FB_DIV
DIV_SELA1, DIV_SELB0
-5
V
IN = 0V
Input
Low Current
IIL
DIV_SELB1, DIV_SELA0,
VCO_SEL, XTAL_SEL,
CLK_ENA, CLK_ENB
V
DD = 3.465V or 2.625V,
-150
VIN = 0V
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REV.B AUGUST 25, 2005
5
PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
VOD
Differential Output Voltage
350
0
mV
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
40
50
mV
V
1.4
0
Δ VOS
VOS Magnitude Change
mV
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Fundamental
FB_DIV = ÷20
Frequency
28
35
29.16
50
MHz
MHz
Ω
FB_DIV = ÷24
23.33
Equivalent Series Resistance (ESR)
Shunt Capacitance
7
pF
Drive Level
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO_A = VDDO_B = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Output Divider = ÷1
Output Divider = ÷2
Output Divider = ÷4
Output Divider = ÷5
Minimum Typical Maximum Units
560
280
140
112
700
350
175
140
MHz
MHz
MHz
MHz
ps
fOUT
Output Frequency Range
tsk(b)
tsk(o)
Bank Skew, NOTE 1
3
Outputs @ Same Frequency
Outputs @ Different Frequencies
625MHz (1.875MHz - 20MHz)
312.5MHz (1.875MHz - 20MHz)
156.25MHz (1.875MHz - 20MHz)
125MHz (1.875MHz - 20MHz)
20ꢀ to 80ꢀ
15
ps
Output Skew; NOTE 2, 4
30
ps
0.55
0.59
0.63
0.64
325
50
ps
ps
RMS Phase Jitter (Random);
NOTE 3
tjit(Ø)
ps
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
ps
ꢀ
NOTE 1: Defined as skew within a bank of outputs at the same voltages and with equal load conditions.
NOTE 2: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at the output differential cross points.
NOTE 3: Please refer to the Phase Noise Plots.
NOTE 4: This parameter is defined in accordance with JEDEC Standard 65.
844003AGI
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REV.B AUGUST 25, 2005
6
PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 156.25MHZ
0
-10
-20
-30
10Gb Ethernet Filter
-40
-50
-60
156.25MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.63ps (typical)
-70
-80
Raw Phase Noise Data
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
10Gb Ethernet Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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REV.B AUGUST 25, 2005
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PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
Phase Noise Plot
VDD
SCOPE
Qx
Power Supply
Float GND
Phase Noise Mask
LVDS
+
-
nQx
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQA0,
nQB0, nQB1
nQx
Qx
QA0,
QB0, QB1
tPW
tPERIOD
nQy
tPW
Qy
odc =
x 100ꢀ
tsk(o)
tPERIOD
OUTPUT SKEW
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
nQB0
QB0
80ꢀ
80ꢀ
tR
VSWING
20ꢀ
Clock
Outputs
20ꢀ
nQB1
tF
QB1
tsk(b)
OUTPUT RISE/FALL TIME
BANK SKEW
VDD
VDD
out
➤
out
➤
DC Input
LVDS
LVDS
DC Input
100
V
OD/Δ VOD
➤
out
out
VOS/Δ VOS
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSET VOLTAGE SETUP
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REV.B AUGUST 25, 2005
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PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844003I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL. VDD, VDDA, and VDDOx
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
were determined using a 31.25MHz or 26.041666MHz 18pF paral-
lel resonant crystal and were chosen to minimize the ppm error.
The ICS844003I has been characterized with 18pF parallel
resonant crystals.The capacitor values shown in Figure 3 below
XTAL_OUT
C1
22p
X1
18pF Parallel Crystal
XTAL_IN
C2
22p
ICS844003I
Figure 3. CRYSTAL INPUt INTERFACE
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REV.B AUGUST 25, 2005
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PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVDS
For applications not requiring the use of the crystal oscillator
All unused LVDS output pairs can be either left floating or
input, both XTAL_IN and XTAL_OUT can be left floating. terminated with 100Ω across. If they are left floating, we
Though not required, but for additional protection, a 1kΩ recommend that there is no trace attached.
resistor can be tied from XTAL_IN to ground.
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the TEST_CLK to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
require a matched load termination of 100Ω across near
the receiver input.
differential transmission line environment, LVDS drivers
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVER TERMINATION
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REV.B AUGUST 25, 2005
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PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS844003I is: 3394
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REV.B AUGUST 25, 2005
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PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 8. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
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REV.B AUGUST 25, 2005
12
PRELIMINARY
ICS844003I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
FREQUENCY SYNTHESIZER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
24 Lead TSSOP
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS844003AGI
ICS844003AGIT
ICS844003AGILF
ICS844003AGITLF
ICS844003AGI
ICS844003AGI
TBD
24 Lead
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or
for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal
commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended
without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in
life support devices or critical medical instruments.
844003AGI
www.icst.com/products/hiperclocks.html
REV.B AUGUST 25, 2005
13
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