ICS844004AGI-04LF [ICSI]
FEMTOCLOCKS? CRYSTAL/LVCMOS-TO-LVDS FREQUENCY SYNTHESIZER; FEMTOCLOCKS ？ CRYSTAL / LVCMOS - TO- LVDS频率合成器
| 型号： | ICS844004AGI-04LF |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL/LVCMOS-TO-LVDS FREQUENCY SYNTHESIZER |
| 文件： | 总13页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS844004I-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS844004I-04 is a 4 output LVDS • Four LVDS outputs
ICS
HiPerClockS™
Synthesizer optimized to generate clock
frequencies for a variety of high performance
• Selectable crystal oscillator interface
or LVCMOS/LVTTL single-ended input
applications and is
a member of the
HiPerClocksTM family of high performance
• Supports the following applications: SONET/SDH, SATA,
or 10Gb Ethernet
clock solutions from ICS. This device can select its input
reference clock from either a crystal input or a single-
ended clock signal. It can be configured to generate 4
outputs with individually selectable divide-by-one or
divide-by-four function via the 4 frequency select pins
(F_SEL[3:0]). The ICS844004I-04 uses ICS’ 3rd generation
low phase noise VCO technology and can achieve 1ps
or lower typical rms phase jitter. This ensures that it
will easily meet clocking requirements for SDH (STM-1/
STM-4/STM-16) and SONET (OC-3/OC12/OC-48). This
device is suitable for multi-rate and multiple port line
card applications. The ICS844004I-04 is conveniently
packaged in a small 24-pin TSSOP package.
• Output frequency range: 140MHz - 170MHz,
560MHz - 680MHz
• VCO range: 560MHz - 680MHz
• Crystal oscillator and CLK range: 17.5MHz - 21.25MHz
• RMS phase jitter @ 622.08MHz output, using a 19.44MHz
crystal (12kHz - 20MHz): 0.71ps (typical)
• RMS phase jitter @ 156.25MHz output, using a 19.53125MHz
crystal (1.875MHz - 20MHz): 0.51ps (typical)
• RMS phase jitter @ 155.52MHz output, using a 19.44MHz
crystal (12kHz - 5MHz): 0.75ps (typical)
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
PIN ASSIGNMENT
BLOCK DIAGRAM
XTAL_IN
nQ1
Q1
VDDo
Q0
1
2
3
4
5
6
7
8
24
23
22
nQ2
Q2
VDDO
Q3
OSC
0
÷1
÷4
0
1
Q0
XTAL_OUT
CLK
nQ0
21
20
19
18
17
16
15
14
13
Phase
Detector
VCO
Pulldown
nQ0
MR
F_SEL3
nc
nQ3
GND
F_SEL2
INPUT_SEL
CLK
1
Pulldown
INPUT_SEL
M = ÷32
9
VDDA
Pulldown
Pullup
10
11
12
F_SEL0
VDD
GND
XTAL_IN
MR
Q1
0
1
F_SEL0
F_SEL1
XTAL_OUT
nQ1
Pullup
Pullup
Pullup
ICS844004I-04
24-LeadTSSOP
4.40mm x 7.8mm x 0.92mm
package body
F_SEL1
Q2
0
1
nQ2
G Package
TopView
F_SEL2
F_SEL3
Q3
0
1
nQ3
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844004AGI-04
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REV.A JANUARY 26, 2006
1
PRELIMINARY
ICS844004I-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
nQ1, Q1
VDDO
Type
Output
Description
Differential output pair. LVDS interface levels.
Output supply pins.
3, 22
4, 5
Power
Ouput
Q0, nQ0
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs nQx
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
6
MR
Input
Input
Pulldown
7,
F_SEL3,
F_SEL0,
F_SEL1,
F_SEL2
10,
12,
18
Pullup Frequency select pins. LVCMOS/LVTTL interface levels. See Table 3.
8
nc
VDDA
VDD
Unused
Power
Power
No connect.
9
Analog supply pin.
Core supply pin.
11
XTAL_OUT,
XTAL_IN
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
13, 14
Input
15, 19
16
GND
CLK
Power
Input
Power supply ground.
Pulldown LVCMOS/LVTTL clock input.
Selects between crystal or CLK inputs as the the PLL Reference source.
Pulldown Selects XTAL inputs when LOW. Selects CLK when HIGH.
LVCMOS/LVTTL interface levels.
17
INPUT_SEL
Input
20, 21
23, 24
nQ3, Q3
Q2, nQ2
Output
Output
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
NOTE: Pulldown and Pullup refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
RPULLUP Input Pullup Resistor
51
51
TABLE 3. OUTPUT CONFIGURATION AND FREQUENCY RANGE FUNCTION TABLE
Inputs
XTAL (MHz)
N Divider Value Output Frequency (MHz)
VCO
(MHz)
Application
F_SELx
N0:N3
Q0/nQ0:Q3/nQ3
622.08
155.52
600
0
1
0
1
0
1
0
1
19.44
19.44
622.08
622.08
600
1
4
1
4
1
4
1
4
SONET/SDH
SATA
18.75
18.75
600
150
19.53125
19.53125
20.141601
20.141601
625
625
10 Gigabit Ethernet
625
156.25
644.5312
161.13
644.5312
644.5312
10 Gigabit Ethernet
66B/64B FEC
844004AGI-04
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REV.A JANUARY 26, 2006
2
PRELIMINARY
ICS844004I-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
CC
Inputs, V
-0.5V to VCC + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
PackageThermal Impedance, θ
70°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
80
8
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
87
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
0.8
V
V
Input Low Voltage
-0.3
CLK,
MR, INPUT_SEL
VDD = VIN = 3.465
150
5
µA
µA
µA
IIH
Input High Current
F_SEL0:F_SEL3
VDD = VIN = 3.465
CLK,
MR, INPUT_SEL
VDD = 3.465V, VIN = 0V
-5
IIL
Input Low Current
Input Edge Rate
F_SEL0:F_SEL3
CLK
VDD = 3.465V, VIN = 0V
20ꢀ - 80ꢀ
-150
µA
ΔV/ΔT
TBD
V/ns
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum
Typical
350
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
40
1.35
50
Δ VOS
VOS Magnitude Change
mV
844004AGI-04
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REV.A JANUARY 26, 2006
3
PRELIMINARY
ICS844004I-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
17.5
21.25
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
NOTE: Characterized using an 18pF parallel resonant crystal.
TABLE 6. AC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Output Divider = ÷1
Output Divider = ÷4
Minimum Typical Maximum Units
560
140
680
170
MHz
MHz
ps
fOUT
Output Frequency
tsk(o)
Output Skew; NOTE 1, 2
TBD
0.75
155.52MHz,
Integration Range: 12kHz - 20MHz
156.25MHz,
Integration Range: 1.875MHz - 20MHz
622.08MHz,
Integration Range: 12kHz - 20MHz
ps
ps
ps
RMS Phase Jitter (Random);
NOTE 3
tjit(Ø)
0.51
0.71
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
290
50
ps
ꢀ
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDDO/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
844004AGI-04
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REV.A JANUARY 26, 2006
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PRELIMINARY
ICS844004I-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 155.52MHZ AT 3.3V
0
-10
-20
-30
-40
-50
OC3 SONET Filter
155.52MHz
RMS Phase Jitter (Random)
12kHz to 5MHz = 0.75ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
Phase Noise Result by adding
OC3 SONET Filter to raw data
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 622.08MHZ AT 3.3V
0
-10
-20
-30
OC 12 SONET Filter
-40
-50
622.08MHz
RMS Phase Jitter (Random)
-60
12kHz to 20MHz = 0.71ps (typical)
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
Phase Noise Result by adding
OC 12 SONET Filter to raw data
-170
-180
-190
10
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
844004AGI-04
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REV.A JANUARY 26, 2006
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PRELIMINARY
ICS844004I-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VDD
nQx
SCOPE
Qx
Qx
Power Supply
Float GND
nQy
Qy
LVDS
+
-
nQx
tsk(o)
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
OUTPUT SKEW
Phase Noise Plot
nQ0:nQ3
Q0:Q3
tPW
Phase Noise Mask
tPERIOD
tPW
odc =
x 100ꢀ
Offset Frequency
f1
f2
tPERIOD
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
out
80ꢀ
tF
80ꢀ
tR
➤
DC Input
LVDS
VSWING
20ꢀ
Clock
Outputs
20ꢀ
out
VOS/Δ VOS
➤
OUTPUT RISE/FALL TIME
OFFSET VOLTAGE SETUP
VDD
➤
out
out
LVDS
DC Input
100
V
OD/Δ VOD
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844004AGI-04
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REV.A JANUARY 26, 2006
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PRELIMINARY
ICS844004I-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS844004I-04 provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD, VDDA, and VDDO
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844004I-04 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using a 19.44MHz 18pF
parallel resonant crystal and were chosen to minimize
the ppm error.
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
ICS844004I-04
Figure 2. CRYSTAL INPUt INTERFACE
844004AGI-04
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REV.A JANUARY 26, 2006
7
PRELIMINARY
ICS844004I-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
OUTPUTS:
CRYSTAL INPUT:
LVDS
For applications not requiring the use of the crystal oscillator All unused LVDS outputs can be left floating. We recommend
input, both XTAL_IN and XTAL_OUT can be left floating. that there is no trace attached. Both sides of the differential
Though not required, but for additional protection, a 1kΩ output pair should either be left floating or terminated.
resistor can be tied from XTAL_IN to ground.
CLK INPUT:
For applications not requiring the use of a clock input, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
LVCMOS CONTROL PINS:
All control pins have internal pull-ups or pull-downs; additional
resistance is not required but can be added for additional
protection. A 1kΩ resistor can be used.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if
only partial outputs are used, it is recommended to termi-
nate the unused outputs.
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
844004AGI-04
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REV.A JANUARY 26, 2006
8
PRELIMINARY
ICS844004I-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
SCHEMATIC EXAMPLE
Figure 4 shows a schematic example for ICS844004i-04. In this Each decoupling capacitor should be located as close as
example, the input is a 19.44MHz parallel resonant crystal with possible to the power pin. The low pass filter R2, C3 and C4
load capacitor CL=18pF. The 22pF frequency fine tuning should also be located as close to the VCCA pin as possible.
capacitors are used C1 and C2.This example also shows general For LVDS driver, the unused output pairs should be terminated
logic control input handling. For decoupling capacitors, it is with a 100Ω resistor across.
recommended to have one decouple capacitor per power pin.
VCC
VCCA
R2
10
Zo = 50 Ohm
Zo = 50 Ohm
C3
10uF
C4
0.01u
+
-
VCC
VCCO
R3
100
C6
0.1u
C7
0.1u
Logic Control Input Examples
Set Logic
Input to
'1'
Set Logic
Input to
'0'
VCC
VCC
RU1
1K
RU2
Not Install
To Logic
Input
pins
To Logic
Input
pins
VCC=3.3V
VCCO=3.3V
U1
RD1
Not Install
RD2
1K
844004i-04
Zo = 50 Ohm
Zo = 50 Ohm
+
-
R4
100
X1
VCCO
C2
33pF
19.44MHz
18pF
C8
0.1u
C9
C1
27pF
0.1u
FIGURE 4. ICS844004I-04 SCHEMATIC EXAMPLE
844004AGI-04
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REV.A JANUARY 26, 2006
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PRELIMINARY
ICS844004I-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844004I-04.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844004I-04 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
•
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (80mA + 8mA) = 304.92mW
Power (outputs)MAX = VDDO_MAX * IDDO_MAX = 3.465V * 87mA = 301.45mW
Total Power_MAX = 304.92mW + 301.45mW = 606.37mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability
of the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
qJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 1 meter per second and a multi-layer board, the appropriate value is 65°C/W per Table 7
below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.606W * 65°C/W = 124°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 24-LEADTSSOP, FORCED CONVECTION
θ
JA by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
844004AGI-04
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PRELIMINARY
ICS844004I-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOWT ABLE FOR 24 LEADTSSOP
θ
JA by Velocity (Meters per Second)
0
1
2.5
Multi-Layer PCB, JEDEC Standard Test Boards
70°C/W
65°C/W
62°C/W
TRANSISTOR COUNT
The transistor count for ICS844004I-04 is: 2285
844004AGI-04
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ICS844004I-04
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 24 LEAD TSSOP
TABLE 9. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
24
--
1.20
0.15
1.05
0.30
0.20
7.90
A1
A2
b
0.05
0.80
0.19
0.09
7.70
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
844004AGI-04
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ICS844004I-04
Integrated
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Systems, Inc.
FEMTOCLOCKS™ CRYSTAL/LVCMOS-TO-
LVDS FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS844004AGI-04
ICS844004AGI-04T
ICS844004AGI-04LF
ICS844004AGI-04LFT
ICS844004AI04
ICS844004AI04
ICS44004AI04L
ICS44004AI04L
24 Lead TSSOP
24 Lead TSSOP
2500 tape & reel
tube
24 Lead "Lead-Free" TSSOP
24 Lead "Lead-Free" TSSOP
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FEMTOCLOCKS are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
844004AGI-04
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REV.A JANUARY 26, 2006
13
相关型号：
SI9130DB
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