ICS844008AYI-15T [ICSI]
FEMTOCLOCKS? CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER; FEMTOCLOCKS ™ CRYSTAL - TO- LVDS频率合成器
| 型号： | ICS844008AYI-15T |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO-LVDS FREQUENCY SYNTHESIZER |
| 文件： | 总12页 (文件大小：145K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS844008I-15
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
The ICS844008I-15 is an 8 output LVDS • Eight LVDS outputs
ICS
HiPerClockS™
Synthesizer optimized to generate PCI Express
• Crystal oscillator interface
reference clock frequencies and is a member
• Supports the following output frequencies:
100MHz or 125MHz
of the HiPerClocksTM family of high performance
clock solutions from ICS. Using a 25MHz
• VCO: 500MHz
parallel resonant crystal, the following frequencies can be
generated based on F_SEL pin: 100MHz or 125MHz. The
ICS844008I-15 uses ICS’ 3rd generation low phase noise
VCO technology and can achieve <1ps typical rms phase
jitter, easily meeting PCI Express jitter requirements. The
ICS844008I-15 is packaged in a 32-pin LQFP package.
• RMS phase jitter @ 125MHz, using a 25MHz crystal
(1.875MHz - 20MHz): 0.42ps (typical)
• Full 3.3V supply modes
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS compliant
packages
PIN ASSIGNMENT
FREQUENCY SELECT FUNCTIONTABLE
Input
Input
Output
Frequency
(MHz)
M Divider N Divider M/N Divider Frequency
32 31 30 29 28 27 26 25
F_SEL
Value
Value
Value
(MHz)
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
Q0
nQ0
VDD
Q1
Q7
25MHz
0
20
4
5
125
nQ7
VDD
Q6
25MHz
1
20
5
4
100
ICS844008I-15
32-Lead LQFP
7mm x 7mm x 1.4mm
package body
Y Package
nQ1
GND
Q2
nQ6
GND
Q5
BLOCK DIAGRAM
Q0
Pulldown
Top View
nPLL_SEL
nQ0
Q1
nQ2
nQ5
9
10 11 12 13 14 15 16
nQ1
Q2
1
0
25MHz
VCO
500MHz
(w/25MHz
Reference)
XTAL_IN
Phase
Detector
÷4
÷5
nQ2
Q3
OSC
XTAL_OUT
nQ3
Q4
M =
÷
20 (fixed)
nQ4
Q5
Pullup
OE1
nQ5
Q6
nQ6
Q7
nQ7
Pulldown
MR
Pullup
F_SEL
Pullup
OE2
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
844008AYI-15
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REV.A FEBRUARY 2, 2006
1
PRELIMINARY
ICS844008I-15
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
TABLE 1. PIN DESCRIPTIONS
Number
Name
Type
Output
Description
1, 2
Q0, nQ0
Differential output pair. LVDS interface levels.
3, 12,
22, 27
VDD
Power
Ouput
Power
Core supply pin.
4, 5
Q1, nQ1
GND
Differential output pair. LVDS interface levels.
Power supply ground.
6, 13,
19, 29
7, 8
9
Q2, nQ2
F_SEL
Output
Input
Differential output pair. LVDS interface levels.
Pullup Frequency select pin LVCMOS/LVTTL interface levels.
Differential output pair. LVDS interface levels.
10, 11
14, 15
Q3, nQ3
Q4, nQ4
Output
Output
Differential output pair. LVDS interface levels.
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
Pulld- causing the true outputs Qx to go low and the inverted outputs nQx
16
MR
Input
own
to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS/LVTTL interface levels.
17, 18
20, 21
23, 24
25
nQ5, Q5
nQ6, Q6
nQ7, Q7
VDDA
Output
Output
Output
Power
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Analog supply pin.
Selects between the PLL and REF_CLK as input to the dividers. When LOW,
selects PLL (PLL Enable). When HIGH, deselects the reference clock (PLL
Bypass). LVCMOS/LVTTL interface levels.
Pulld-
own
26
nPLL_SEL
Input
Output enable for Q5/nQ5:Q7/nQ7 outputs.
LVCMOS/LVTTL interface levels.
Parallel resonant crystal interface. XTAL_OUT is the output,
XTAL_IN is the input.
Output enable for Q0/nQ0:Q4/nQ4 outputs.
LVCMOS/LVTTL interface levels.
28
30, 31
32
OE2
Input
Input
Input
Pullup
XTAL_OUT,
XTAL_IN
OE1
Pullup
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
RPULLUP Input PullUP Resistor
51
51
TABLE 3A. OE1 FUNCTIONT ABLE
TABLE 3B. OE2 FUNCTIONT ABLE
Input Outputs
Input Outputs
OE1 Q0:Q4, nQ0:nQ4
OE2 Q5:Q7, nQ5:nQ7
0
1
Places outputs in Hi-Z state
Normal operation
0
1
Places outputs in Hi-Z state
Normal operation
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REV.A FEBRUARY 2, 2006
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PRELIMINARY
ICS844008I-15
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA 47.9°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 4A. POWER SUPPLY DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
3.135
3.135
3.3
3.3
122
11
3.465
3.465
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
V
mA
mA
IDDA
TABLE 4B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
VDD = 3.3V
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
Input Low Voltage
2
VDD + 0.3
V
VDD = 3.3V
-0.3
0.8
150
5
V
MR, nPLL_SEL
VDD = VIN = 3.465
µA
µA
µA
µA
Input
High Current
IIH
OE1, OE2, F_SEL
MR, nPLL_SEL
VDD = VIN = 3.465
VDD = 3.465V, VIN = 0V
VDD = 3.465V, VIN = 0V
-5
Input
Low Current
IIL
OE1, OE2, F_SEL
-150
TABLE 4C. LVDS DC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions
Minimum
Typical
350
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
40
1.25
50
Δ VOS
VOS Magnitude Change
mV
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REV.A FEBRUARY 2, 2006
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PRELIMINARY
ICS844008I-15
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
TABLE 5. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
25
Mode of Oscillation
Frequency
22.4
27.2
100
50
MHz
ppm
Ω
Parts per Million (ppm); NOTE 1
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
7
pF
100
µW
NOTE: Characterized using an18pF parallel resonant crystal.
NOTE 1: When used with recommended 50ppm crystal and external trim caps adjusted for user PC board.
TABLE 6. AC CHARACTERISTICS, VDD = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
FSEL = 0
Minimum Typical Maximum Units
125
100
TBD
25
MHz
MHz
ps
fOUT
Output Frequency
FSEL = 1
tsk(o)
tjit(cc)
Output Skew; NOTE 1, 2
Cycle-to-Cycle Jitter
50
50
1
ps
125MHz, (1.875MHz - 20MHz)
100MHz, (1.875MHz - 20MHz)
20ꢀ to 80ꢀ
0.42
0.46
330
50
ps
RMS Phase Jitter (Random);
NOTE 3
tjit(Ø)
1
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
200
48
650
52
ps
ꢀ
Minimum and Maximum values are design target specs.
NOTE 1: Defined as skew between outputs at the same supply voltages and with equal load conditions.
Measured at VDD/2.
NOTE 2: This parameter is defined in accordance with JEDEC Standard 65.
NOTE 3: Please refer to the Phase Noise Plot.
844008AYI-15
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REV.A FEBRUARY 2, 2006
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PRELIMINARY
ICS844008I-15
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
TYPICAL PHASE NOISE AT 125MHZ AT 3.3V
0
-10
-20
-30
-40
-50
-60
PCI Express Jitter Filter
125MHz
RMS Phase Jitter (Random)
1.875Mhz to 20MHz = 0.42ps (typical)
-70
-80
-90
-100
-110
-120
Raw Phase Noise Data
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
PCI Express Filter to raw data
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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REV.A FEBRUARY 2, 2006
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PRELIMINARY
ICS844008I-15
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
Phase Noise Plot
SCOPE
Qx
3.3V 5ꢀ
POWER SUPPLY
LVDS
+
Float GND
-
Phase Noise Mask
nQx
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
3.3V CORE/3.3V OUTPUT LOAD AC TEST CIRCUIT
RMS PHASE JITTER
nQ0:nQ7
Q0:nQ7
nQx
Qx
➤
➤
tcycle n
tcycle n+1
➤
➤
nQy
Qy
tjit(cc) = tcycle n –tcycle n+1
tsk(o)
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nQ0:nQ7
80ꢀ
tF
80ꢀ
Q0:Q7
VSWING
tPW
Clock
Outputs
20ꢀ
20ꢀ
tPERIOD
tR
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
OUTPUT RISE/FALLTIME
VDD
VDD
out
➤
out
out
➤
DC Input
LVDS
LVDS
V
OD/Δ VOD
DC Input
100
➤
out
VOS/Δ VOS
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OFFSETVOLTAGE SETUP
844008AYI-15
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REV.A FEBRUARY 2, 2006
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PRELIMINARY
ICS844008I-15
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844008I-15 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. VDD and VDDA
should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
capacitor should be connected to each VDDA
.
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844008I-15 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 2 below were determined using a 25MHz parallel
resonant crystal and were chosen to minimize the ppm error.
XTAL_OUT
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
C2
27p
Figure 2. CRYSTAL INPUt INTERFACE
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REV.A FEBRUARY 2, 2006
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PRELIMINARY
ICS844008I-15
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
LVCMOS CONTROL PINS:
OUTPUTS:
LVDS
All control pins have internal pull-ups or pull-downs; additional All unused LVDS output pairs can be either left floating or
resistance is not required but can be added for additional terminated with 100Ω across. If they are left floating, we
protection. A 1kΩ resistor can be used.
recommend that there is no trace attached.
3.3V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if
only partial outputs are used, it is recommended to termi-
nate the unused outputs.
3.3V
3.3V
LVDS
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVERT ERMINATION
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REV.A FEBRUARY 2, 2006
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PRELIMINARY
ICS844008I-15
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
POWER CONSIDERATIONS
This section provides information on power dissipation and junction temperature for the ICS844008I-15.
Equations and example calculations are also provided.
1. Power Dissipation.
The total power dissipation for the ICS844008I-15 is the sum of the core power plus the power dissipated in the load(s).
The following is the power dissipation for VDD = 3.3V + 5ꢀ = 3.465V, which gives worst case results.
•
Power (core)MAX = VDD_MAX * (IDD_MAX + IDDA_MAX) = 3.465V * (122mA + 11mA) = 460.85mW
2. Junction Temperature.
Junction temperature, Tj, is the temperature at the junction of the bond wire and bond pad and directly affects the reliability of
the device. The maximum recommended junction temperature for HiPerClockSTM devices is 125°C.
The equation for Tj is as follows: Tj = θJA * Pd_total + TA
Tj = Junction Temperature
θJA = Junction-to-Ambient Thermal Resistance
Pd_total = Total Device Power Dissipation (example calculation is in section 1 above)
TA = Ambient Temperature
In order to calculate junction temperature, the appropriate junction-to-ambient thermal resistance θJA must be used.
Assuming a moderate air flow of 200 linear feet per minute and a multi-layer board, the appropriate value is 42.1°C/W per
Table 7 below.
Therefore, Tj for an ambient temperature of 85°C with all outputs switching is:
85°C + 0.461W * 42.1°C/W = 104.4°C. This is below the limit of 125°C.
This calculation is only an example. Tj will obviously vary depending on the number of loaded outputs, supply voltage, air
flow, and the type of board (single layer or multi-layer).
TABLE 7. THERMAL RESISTANCE θJA FOR 32-LEAD LQFP, FORCED CONVECTION
θ
JA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
844008AYI-15
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REV.A FEBRUARY 2, 2006
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PRELIMINARY
ICS844008I-15
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
RELIABILITY INFORMATION
TABLE 8. θJAVS. AIR FLOWTABLE FOR 32 LEAD LQFP
θ
JA by Velocity (Linear Feet per Minute)
0
200
55.9°C/W
42.1°C/W
500
50.1°C/W
39.4°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
67.8°C/W
47.9°C/W
NOTE: Most modern PCB designs use multi-layered boards. The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS844008I-15 is: TBD
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REV.A FEBRUARY 2, 2006
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PRELIMINARY
ICS844008I-15
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
PACKAGE OUTLINE -Y SUFFIX FOR 32 LEAD LQFP
TABLE 9. PACKAGE DIMENSIONS
JEDEC VARIATION
ALL DIMENSIONS IN MILLIMETERS
BBA
SYMBOL
MINIMUM
NOMINAL
MAXIMUM
N
A
32
--
--
--
1.60
0.15
1.45
0.45
0.20
A1
A2
b
0.05
1.35
0.30
0.09
1.40
0.37
c
--
D
9.00 BASIC
7.00 BASIC
5.60 Ref.
9.00 BASIC
7.00 BASIC
5.60 Ref.
0.80 BASIC
0.60
D1
D2
E
E1
E2
e
L
0.45
0.75
θ
--
0°
7°
ccc
--
--
0.10
Reference Document: JEDEC Publication 95, MS-026
844008AYI-15
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PRELIMINARY
ICS844008I-15
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-
LVDS FREQUENCY SYNTHESIZER
TABLE 10. ORDERING INFORMATION
Part/Order Number
ICS844008AYI-15
Marking
ICS44008AI15
ICS44008AI15
TBD
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
32 Lead LQFP
ICS844008AYI-15T
ICS844008AYI-15LF
ICS844008AYI-15LFT
32 Lead LQFP
1000 tape & reel
tube
32 Lead "Lead-Free" LQFP
32 Lead "Lead-Free" LQFP
TBD
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant.
The ICS logo is a registered trademark, and HiPerClockS is a trademark of Integrated Circuit Systems, Inc. All other trademarks are the property of their respective owners and may be registered
in certain jurisdictions.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use or for infringement
of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in normal commercial and industrial
applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without additional processing by ICS. ICS reserves
the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical medical instruments.
844008AYI-15
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REV.A FEBRUARY 2, 2006
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