ICS844051CGIT [ICSI]
FEMTOCLOCKS? CRYSTAL-TO- LVDS CLOCK GENERATOR; FEMTOCLOCKS ？ CRYSTAL - TO- LVDS时钟发生器
| 型号： | ICS844051CGIT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO- LVDS CLOCK GENERATOR |
| 文件： | 总11页 (文件大小：202K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS844051I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
• One Differential LVDS output
The ICS844051I is a Gigabit Ethernet Clock
ICS
HiPerClockS™
Generator and a member of the HiPerClocksTM
family of high performance devices from ICS.
The ICS844051I can synthesize 10 Gigabit
Ethernet, SONET, or Serial ATA reference clock
• Crystal oscillator interface designed for
18pF parallel resonant crystals (18.125MHz - 23.4375MHz)
• Output frequency range: 145MHz - 187.5MHz and
72.5MHz - 93.75MHz
frequencies with the appropriate choice of crystal and output
divider. The ICS844051I has excellent phase jitter perfor-
mance and is packaged in a small 8-pin TSSOP, making it
ideal for use in systems with limited board space.
• VCO range: 580MHz - 750MHz
• RMS phase jitter @156.25MHz (1.875MHz - 20MHz):
0.45ps (typical)
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-compliant
packages
FREQUENCY TABLE
Inputs
Output Frequency
(MHz)
Crystal Frequency (MHz)
20.141601
20.141601
19.53125
19.53125
19.44
FREQ_SEL
0
1
0
1
0
1
0
1
161.132812
80.566406
156.25
78.125
155.52
77.76
19.44
18.75
150
18.75
75
BLOCK DIAGRAM
PIN ASSIGNMENT
Pulldown
FREQ_SEL
VDDA
GND
VDD
1
2
3
4
8
7
6
5
Q
XTAL_IN
OSC
0 ÷4 (default)
1 ÷8
Q
Phase
Detector
XTAL_OUT
XTAL_IN
nQ
VCO
nQ
FREQ_SEL
XTAL_OUT
ICS844051I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
÷32
(fixed)
G Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
844051CGI
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REV.A NOVEMBER 23, 2005
1
PRELIMINARY
ICS844051I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDA
Type
Description
1
2
Power
Power
Analog supply pin.
GND
Power supply ground.
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
3, 4
Input
5
6, 7
8
FREQ_SEL
nQ, Q
Input
Output
Power
Pullup
Frequency select pin.
Differential clock outputs. LVDS interface levels.
Power supply pin.
VDD
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
RPULLUP
51
kΩ
844051CGI
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REV.A NOVEMBER 23, 2005
2
PRELIMINARY
ICS844051I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5 V
I
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
PackageThermal Impedance, θ
101.7°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
IDD
Power Supply Voltage
3.465
3.465
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
100
8
mA
mA
IDDA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VDD
VDDA
IDD
Power Supply Voltage
2.625
2.625
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
2.375
2.5
V
95
mA
mA
IDDA
8
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
DD = 3.3V
VDD = 2.5
V
2
VDD + 0.3
VDD + 0.3
0.8
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
V
DD = 3.3V
V
Input Low Voltage
VDD = 2.5
0.7
V
IIH
IIL
Input High Current
Input Low Current
VDD = VIN = 3.465V or 2.625V
VDD = 3.465V or 2.625V, VIN = 0V
5
µA
µA
-150
844051CGI
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REV.A NOVEMBER 23, 2005
3
PRELIMINARY
ICS844051I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 3D. LVDS DC CHARACTERISTICS, VDD =VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum
Typical
350
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
400
1.4
Δ VOS
VOS Magnitude Change
50
mV
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
350
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
400
1.15
40
Δ VOS
VOS Magnitude Change
mV
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
18.125
23.4375
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
1
mW
TABLE 5A. AC CHARACTERISTICS, VDD =VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
156.25
MHz
RMS Phase Jitter ( Random);
NOTE 1
156.25MHz @ Integration Range:
1.875MHz - 20MHz
tjit(Ø)
0.45
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
300
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plots following this section.
TABLE 5B. AC CHARACTERISTICS, VDD =VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
156.25
MHz
RMS Phase Jitter ( Random);
NOTE 1
156.25MHz @ Integration Range:
1.875MHz - 20MHz
tjit(Ø)
0.45
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
300
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plots following this section.
844051CGI
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REV.A NOVEMBER 23, 2005
4
PRELIMINARY
ICS844051I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TYPICAL PHASE NOISE AT 156.25MHZ @ 3.3V
0
-10
Gb Ethernet Filter
-20
-30
-40
156.25MHz
RMS Phase Jitter (Random)
-50
1.875MHz to 20MHz = 0.45ps (typical)
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Gb Ethernet Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 156.25MHZ @ 2.5V
0
-10
-20
-30
-40
Gb Ethernet Filter
156.25MHz
RMS Phase Jitter (Random)
1.875MHz to 20MHz = 0.45ps (typical)
-50
-60
-70
-80
-90
Raw Phase Noise Data
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
Phase Noise Result by adding
Gb Ethernet Filter to raw data
100
1k
10k
100k
1M
10M
100M
OFFSET FREQUENCY (HZ)
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844051CGI
REV.A NOVEMBER 23, 2005
5
PRELIMINARY
ICS844051I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
SCOPE
Qx
SCOPE
Qx
Power Supply
Float GND
2.5V 5ꢀ
POWER SUPPLY
+
LVDS
Float GND
-
LVDS
+
-
nQx
nQx
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT
Phase Noise Plot
nQ
Q
tPW
tPERIOD
Phase Noise Mask
tPW
tPERIOD
odc =
x 100ꢀ
Offset Frequency
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
out
80ꢀ
tF
80ꢀ
tR
➤
DC Input
LVDS
VSWING
20ꢀ
Clock
Outputs
20ꢀ
out
VOS/Δ VOS
➤
OFFSET VOLTAGE SETUP
OUTPUT RISE/FALL TIME
V
DD
➤
out
out
LVDS
DC Input
100
V
OD/Δ VOD
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844051CGI
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REV.A NOVEMBER 23, 2005
6
PRELIMINARY
ICS844051I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844051I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD and VDDA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin. The 10Ω
resistor can also be replaced by a ferrite bead.
3.3V or 2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844051I has been characterized with 18pF parallel resonant crystal and were chosen to minimize the ppm error.
resonant crystals. The capacitor values, C1 and C2, shown in The optimum C1 and C2 values can be slightly adjusted for dif-
Figure 2 below were determined using a 25MHz, 18pF parallel ferent board layouts.
XTAL_IN
C1
X1
Crystal
XTAL_OUT
C2
Figure 2.CRYSTAL INPUt INTERFACE
844051CGI
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REV.A NOVEMBER 23, 2005
7
PRELIMINARY
ICS844051I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
2.5V or 3.3V
VDD
LVDS_Driver
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
844051CGI
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REV.A NOVEMBER 23, 2005
8
PRELIMINARY
ICS844051I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS844051I is: 2395
844051CGI
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REV.A NOVEMBER 23, 2005
9
PRELIMINARY
ICS844051I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
844051CGI
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REV.A NOVEMBER 23, 2005
10
PRELIMINARY
ICS844051I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS844051CGI
Marking
451CI
451CI
TBD
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
8 Lead TSSOP
ICS844051CGIT
ICS844051CGILF
ICS844051CGILFT
8 Lead TSSOP
2500 tape & reel
tube
8 Lead "Lead-Free" TSSOP
8 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts thar are ordered with an "LF" suffix to the part number are the Pb-Free configuraiton and are RoHS compliant.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
844051CGI
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REV.A NOVEMBER 23, 2005
11
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