ICS844071AGIT [ICSI]
FEMTOCLOCKS? CRYSTAL-TO- LVDS CLOCK GENERATOR; FEMTOCLOCKS ？ CRYSTAL - TO- LVDS时钟发生器
| 型号： | ICS844071AGIT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO- LVDS CLOCK GENERATOR |
| 文件： | 总10页 (文件大小：167K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS844071I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO- LVDS
CLOCK GENERATOR
GENERAL DESCRIPTION
FEATURES
• (1) Differential LVDS output
The ICS844071I is a Serial ATA (SATA)/Serial
ICS
Attached SCSI (SAS) Clock Generator and a
member of the HiPerClocksTM family of high
performance devices from ICS.The ICS844071I
uses an 18pF parallel resonant crystal over the
HiPerClockS™
• Crystal oscillator interface, 18pF parallel resonant crystal
(20.833MHz - 28.3MHz)
• Output frequency range: 62.5MHz - 170MHz
• VCO range: 500MHz - 680MHz
range of 20.833MHz - 28.3MHz. For SATA/SAS applications,
a 25MHz crystal is used and either 75MHz or 150MHz may
be selected with the FREQ_SEL pin. The ICS844071I has
excellent <1ps phase jitter performance, over the 12kHz -
20MHz integration range. The ICS844071I is packaged in a
small 8-pin TSSOP, making it ideal for use in systems with
limited board space.
• RMS phase jitter @ 150MHz, using a 25MHz crystal
(12kHz - 20MHz): 0.75ps (typical)
• 3.3V or 2.5V operating supply
• -40°C to 85°C ambient operating temperature
• Replaces ICS844051-11
COMMON CONFIGURATION TABLE
Inputs
Output Frequency
Multiplication Value
M/N
(MHz)
Crystal Frequency (MHz) FREQ_SEL
M
N
25
0
1
0
1
0
1
24
24
24
24
24
24
4
8
4
8
4
8
6
3
6
3
6
3
150
75
25
26.041666
26.041666
26.5625
26.5625
156.25
78.125
159.375
79.675
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
FREQ_SEL
VDDA
VDD
1
2
3
4
8
7
6
5
GND
Q
XTAL_OUT
XTAL_IN
nQ
FREQ_SEL
N
÷4
÷8
XTAL_IN
OSC
XTAL_OUT
Q
VCO
Phase
Detector
FREQ_SEL
0
1
500MHz - 680MHz
nQ
ICS844071I
8-Lead TSSOP
4.40mm x 3.0mm x 0.925mm
package body
M = ÷24 (fixed)
G Package
TopView
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
844071AGI
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REV. A JULY 13, 2005
1
PRELIMINARY
ICS844071I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 1. PIN DESCRIPTIONS
Number
Name
VDDA
Type
Description
1
2
Power
Power
Analog supply pin.
GND
Power supply ground.
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
3, 4
Input
5
6, 7
8
FREQ_SEL
nQ, Q
Input
Output
Power
Pullup
Frequency select pin. LVCMOS/LVTTL interface levels.
Differential clock outputs. HSTL interface levels.
Core supply pin.
VDD
NOTE: Pullup refers to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol Parameter
Test Conditions
Minimum
Typical Maximum Units
CIN
Input Capacitance
Input Pullup Resistor
4
pF
RPULLUP
51
kΩ
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PRELIMINARY
ICS844071I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO- LVDS
CLOCK GENERATOR
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO (LVDS)
Continuous Current
Surge Current
10mA
15mA
PackageThermal Impedance, θ
101.7°C/W (0 mps)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
3.465
3.465
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
TBD
TBD
mA
mA
IDDA
TABLE 3B. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
2.375
Typical
2.5
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
2.625
2.625
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
2.375
2.5
V
TBD
TBD
mA
mA
IDDA
TABLE 3C. LVCMOS/LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ OR 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units
DD = 3.3V
VDD = 2.5V
DD = 3.3V
V
2
VDD + 0.3
VDD + 0.3
0.8
V
V
VIH
VIL
Input High Voltage
1.7
-0.3
-0.3
V
V
Input Low Voltage
VDD = 2.5V
0.7
V
IIH
IIL
Input High Current FREQ_SEL
VDD = VIN = 3.465V or 2.625V
5
µA
µA
Input Low Current FREQ_SEL VDD = 3.465V or 2.625V, VIN = 0V
-150
NOTE 1: Outputs terminated with 50Ω to VDD/2. See Parameter Measurement Information Section,
"3.3V Output Load Test Circuit".
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REV. A JULY 13, 2005
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PRELIMINARY
ICS844071I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 3D. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum
Typical
350
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
40
1.25
50
Δ VOS
VOS Magnitude Change
mV
TABLE 3E. LVDS DC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
350
50
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
1.2
Δ VOS
VOS Magnitude Change
40
mV
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum
Typical Maximum Units
Fundamental
Mode of Oscillation
Frequency
20.833
28.3
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 5A. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
62.5
170
MHz
150MHz @ Integration Range:
12kHz - 20MHz
75MHz @ Integration Range:
12kHz - 20MHzz
0.75
0.68
ps
RMS Phase Jitter ( Random);
NOTE 1
tjit(Ø)
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
300
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plots following this section.
TABLE 5B. AC CHARACTERISTICS, VDD = VDDA = 2.5V 5ꢀ, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
fOUT
Output Frequency
62.5
170
MHz
150MHz @ Integration Range:
12kHz - 20MHz
75MHz @ Integration Range:
12kHz - 20MHzz
0.96
0.98
ps
RMS Phase Jitter ( Random);
NOTE 1
tjit(Ø)
ps
tR / tF
odc
Output Rise/Fall Time
Output Duty Cycle
20ꢀ to 80ꢀ
300
50
ps
ꢀ
NOTE 1: Please refer to the Phase Noise Plots following this section.
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PRELIMINARY
ICS844071I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO- LVDS
CLOCK GENERATOR
PARAMETER MEASUREMENT INFORMATION
SCOPE
SCOPE
Qx
Qx
2.5V 5ꢀ
3.3V 5ꢀ
POWER SUPPLY
+
POWER SUPPLY
+
LVDS
LVDS
Float GND
-
Float GND
-
nQx
nQx
LVDS 3.3V OUTPUT LOAD AC TEST CIRCUIT
LVDS 2.5V OUTPUT LOAD AC TEST CIRCUIT
nQ
80ꢀ
tF
80ꢀ
tR
Q
VSWING
20ꢀ
tPW
Clock
Outputs
20ꢀ
tPERIOD
tPW
tPERIOD
odc =
x 100ꢀ
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Phase Noise Plot
VDD
out
➤
DC Input
LVDS
Phase Noise Mask
out
VOS/Δ VOS
Offset Frequency
➤
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
OFFSET VOLTAGE SETUP
RMS PHASE JITTER
V
DD
➤
out
out
LVDS
DC Input
100
V
OD/Δ VOD
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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REV. A JULY 13, 2005
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PRELIMINARY
ICS844071I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844071I provides
separate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD and VDDA should
be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 1 illustrates how
a 10Ω resistor along with a 10μF and a .01μF bypass
capacitor should be connected to each VDDA pin.
3.3V or 2.5V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 1. POWER SUPPLY FILTERING
RECOMMENDATIONS FOR UNUSED INPUT AND OUTPUT PINS
INPUTS:
CRYSTAL INPUT:
OUTPUTS:
LVCMOS OUTPUT:
For applications not requiring the use of the crystal oscillator All unused LVCMOS output can be left floating.We recommend
input, both XTAL_IN and XTAL_OUT can be left floating.Though that there is no trace attached.
not required, but for additional protection, a 1kΩ resister can be
tied from XTAL_IN to ground.
LVPECL OUTPUT
All unused LVPECL outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential
CLK INPUT:
For applications not requiring the use of the test clock, it can be output pair should either be left floating or terminated.
left floating.Though not required, but for additional protection, a
1kΩ resister can be tied from the CLK input to ground.
LVHSTL OUTPUT
All unused LVHSTL outputs can be left floating.We recommend
that there is no trace attached. Both sides of the differential
TEST_CLK INPUT:
For applications not requiring the use of the test clock, it can be output pair should either be left floating or terminated.
left floating.Though not required, but for additional protection, a
1kΩ resister can be tied from the TEST_CLK to ground.
LVDS OUTPUT
All unused LVDS outputs should be terminated with 100Ω resister
between the differential pair.
CLK/nCLK INPUT:
For applications not requiring the use of the differential input,
both CLK and nCLK can be left floating. Though not required,
LVDS – Like OUTPUT
but for additional protection, a 1kΩ resister can be tied from CLK All unused LVDS outputs can be left floating. We recommend
to ground.
that there is no trace attached. Both sides of the differential
output pair should either be left floating or terminated.
PCLK/nPCLK INPUT:
For applications not requiring the use of a differential input, both
HCSL OUTPUT
the PCLK and nPCLK pins can be left floating. Though not All unused HCSL outputs can be left floating. We recommend
required, but for additional protection, a 1kΩ resister can be tied that there is no trace attached. Both sides of the differential
from PCLK to ground.
output pair should either be left floating or terminated.
SELECT PINS:
SSTL OUTPUT
All select pins have internal pull-ups and pull-downs; additional All unused SSTL outputs can be left floating. We recommend
resistance is not required but can be added for additional that there is no trace attached. Both sides of the differential
protection. A 1kΩ resister can be used.
output pair should either be left floating or terminated.
844071AGI
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REV. A JULY 13, 2005
6
PRELIMINARY
ICS844071I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO- LVDS
CLOCK GENERATOR
CRYSTAL INPUT INTERFACE
The ICS844071I has been characterized with 18pF parallel resonant crystal and were chosen to minimize the ppm error.
resonant crystals. The capacitor values, C1 and C2, shown in The optimum C1 and C2 values can be slightly adjusted for dif-
ferent board layouts.
Figure 2 below were determined using a 25MHz, 18pF parallel
XTAL_OUT
XTAL_IN
C1
22p
X1
18pF Parallel Crystal
C2
33p
Figure 2. CRYSTAL INPUt INTERFACE
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
un-used outputs.
2.5V or 3.3V
VDD
LVDS_Driv er
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
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REV. A JULY 13, 2005
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PRELIMINARY
ICS844071I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
RELIABILITY INFORMATION
TABLE 6. θJAVS. AIR FLOW TABLE FOR 8 LEAD TSSOP
θJA byVelocity (Meters per Second)
0
1
2.5
89.8°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
101.7°C/W
90.5°C/W
TRANSISTOR COUNT
The transistor count for ICS844071I is: 2533
844071AGI
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REV. A JULY 13, 2005
8
PRELIMINARY
ICS844071I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO- LVDS
CLOCK GENERATOR
PACKAGE OUTLINE - G SUFFIX FOR 8 LEAD TSSOP
TABLE 7. PACKAGE DIMENSIONS
Millimeters
SYMBOL
Minimum
Maximum
N
A
8
--
1.20
0.15
1.05
0.30
0.20
3.10
A1
A2
b
0.05
0.80
0.19
0.09
2.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
844071AGI
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REV. A JULY 13, 2005
9
PRELIMINARY
ICS844071I
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ CRYSTAL-TO- LVDS
CLOCK GENERATOR
TABLE 8. ORDERING INFORMATION
Part/Order Number
ICS844071AGI
Marking
4071A
Package
Shipping Packaging
tube
Temperature
-40°C to 85°C
-40°C to 85°C
8 Lead TSSOP
8 Lead TSSOP
ICS844071AGIT
4071A
2500 tape & reel
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not
recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product
for use in life support devices or critical medical instruments.
844071AGI
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REV. A JULY 13, 2005
10
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