ICS844101AGI-312LFT [ICSI]
FEMTOCLOCKS? CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER; FEMTOCLOCKS ？ CRYSTAL - TO- LVDS 312.5MHZ频率容限合成器
| 型号： | ICS844101AGI-312LFT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | FEMTOCLOCKS? CRYSTAL-TO-LVDS 312.5MHZ FREQUENCY MARGINING SYNTHESIZER |
| 文件： | 总13页 (文件大小：170K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
GENERAL DESCRIPTION
FEATURES
• One 312.5MHz nominal LVDS output
The ICS844101I-312 is a low phase-noise
ICS
frequency margining synthesizer and is a mem-
ber of the HiPerClockS™ family of high perfor-
mance clock solutions from ICS. In the default
mode, the device nominally generates a
• Selectable crystal oscillator interface designed for 25MHz,
18pF parallel resonant crystal or LVCMOS single-ended
input
HiPerClockS™
312.5MHz LVDS output clock signal from a 25MHz crystal • Output frequency can be varied in 2% steps from nominal
input. There is also a frequency margining mode available
where the device can be programmed, using the serial in-
• VCO range: 560MHz - 690MHz
terface, to vary the output frequency up or down from nomi-
nal in 2% steps. The ICS844101I-312 is provided in a 16-
pin TSSOP.
• RMS phase jitter @ 312.5MHz, using a 25MHz crystal
(1.875MHz-20MHz): 0.52ps (typical)
• Output supply modes
Core/Output
3.3V/3.3V
3.3V/2.5V
• -40°C to 85°C ambient operating temperature
• Available in both standard and lead-free RoHS-complaint
packages
BLOCK DIAGRAM
PIN ASSIGNMENT
Pullup
OE
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
GND
S_LOAD
S_DATA
S_CLOCK
SEL
MODE
VDDO
Q
nQ
GND
CLK
XTAL_OUT
XTAL_IN
Pulldown
CLK
1
0
Q
25MHz
Phase
Detector
÷ P
VCO
÷ N
560 - 690MHz
XTAL_IN
nQ
OE
VDDA
OSC
XTAL_OUT
SEL
VDD
Pulldown
÷ M
ICS844101I-312
16-Lead TSSOP
4.4mm x 5.0mm x 0.92mm
package body
Pulldown
S_CLOCK
S_DATA
S_LOAD
MODE
Pulldown
Pulldown
Pulldown
Serial Control
G Package
Top View
The Preliminary Information presented herein represents a product in prototyping or pre-production. The noted characteristics are based on
initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications
without notice.
844101AGI-312
www.icst.com/products/hiperclocks.html
REV.A NOVEMBER 28, 2005
1
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
FUNCTIONAL DESCRIPTION
The ICS844101I-312 features a fully integrated PLL and
therefore requires no external components for setting the
loop bandwidth. A 25MHz fundamental crystal is used as
the input to the on chip oscillator. The output of the oscilla-
tor is fed into the pre-divider. In frequency margining mode,
the 25MHz crystal frequency is divided by 2 and a 12.5MHz
reference frequency is applied to the phase detector. The
VCO of the PLL operates over a range of 560MHz to
690MHz. The output of the M divider is also applied to the
phase detector.
some values of M (either too high or too low), the PLL will
not achieve lock. The output of the VCO is scaled by an
output divider prior to being sent to the LVPECL output
buffer. The divider provides a 50% output duty cycle. The
relationship between the crystal input frequency, the M
divider, the VCO frequency and the output frequency is
provided in Table 1. When changing back from frequency
margining mode to nominal mode, the device will return to
the default nominal configuration that will provide
312.5MHz output frequency.
The default mode for the ICS844101I-312 is 312.5MHz
output frequency using a 25MHz crystal. The output fre-
quency can be changed by placing the device into the
margining mode using the mode pin and using the serial
interface to program the M feedback divider. Frequency
margining mode operation occurs when the MODE input
is HIGH. The phase detector and the M divider force the
VCO output frequency to be M times the reference fre-
quency by adjusting the VCO control voltage. Note that for
Serial operation occurs when S_LOAD is HIGH. Serial data
can be loaded in either the default mode or the frequency
margining mode. The 6-bit shift register is loaded by sam-
pling the S_DATA bits with the rising edge of S_CLOCK.
After shifting in the 6-bit M divider value, S_LOAD is
transitioned from HIGH to LOW which latches the contents of
the shift-register into the M divider control register. When
S_LOAD is LOW, any transitions of S_CLOCK or S_DATA
are ignored.
TABLE 1. FREQUENCY MARGIN FUNCTION TABLE
XTAL Pre-Divider
Reference
Feedback
M-Data
VCO
Output
Output
%
(MHz)
(P)
Frequency (MHz) Divider (M) (Binary) (MHz) Divider (N) Frequency (MHz) Change
25
2
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
12.5
45
46
47
48
49
50
51
52
53
54
55
101101
101110
101111
110000
110001
110010
110011
110100
110101
110110
110111
562.5
575
2
2
2
2
2
2
2
2
2
2
2
281.25
287.5
293.75
300
-10.0
-8.0
-6.0
-4.0
-2.0
0
25
25
25
25
25
25
25
25
25
25
2
2
2
2
2
2
2
2
2
2
587.5
600
612.5
625
306.25
312.5
318.75
325
637.5
650
2.0
4.0
662.5
675
331.25
337.5
343.75
6.0
8.0
687.5
10.0
SERIAL
L
OADING
S_CLOCK
S_DATA
M5 M4 M3 M2 M1 M0
t
t
t
S
H
S
S_LOAD
Time
FIGURE 1. SERIAL LOAD OPERATIONS
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844101AGI-312
REV.A NOVEMBER 28, 2005
2
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 2. PIN DESCRIPTIONS
Νυμ βερ
1, 12
2
Ναμ ε
GND
Τψπε
Δεσχριπτιον
Power supply ground.
Power
Input
S_LOAD
Pulldown Controls the operation of the Serial input. LVCMOS/LVTTL interface levels.
Shift register serial input. Data sampled on the rising edge of S_CLOCK.
LVCMOS/LVTTL interface levels.
Clock in serial data present at S_DATA input into the shift register on the
rising edge of S_CLOCK. LVCMOS/LVTTL interface levels.
Select pin. When HIGH, selects CLK input.
When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels.
Output enable pin. Controls enabling and disabling of Q/nQ outputs.
LVCMOS/LVTTL interface levels
3
4
5
6
S_DATA
S_CLOCK
SEL
Input
Input
Input
Input
Pulldown
Pulldown
Pulldown
OE
Pullup
7
8
VDDA
VDD
Power
Power
Analog supply pin.
Core supply pin.
XTAL_IN,
XTAL_OUT
Parallel resonant crystal interface. XTAL_OUT is the output, XTAL_IN is the
input.
9, 10
Input
11
13, 14
15
CLK
nQ, Q
VDDO
Input
Ouput
Power
Pulldown LVCMOS/LVTTL clock input.
Differential output pair. LVPECL interface levels.
Output supply pin.
MODE pin. LOW = default mode. HIGH = frequency margining mode.
LVCMOS/LVTTL interface levels.
16
MODE
Input
Pulldown
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 3. PIN CHARACTERISTICS
Symbol
Parameter
Test Conditions
Minimum
Typical
Maximum Units
CIN
Input Capacitance
4
pF
kΩ
kΩ
RPULLDOWN Input Pulldown Resistor
51
51
RPULLUP
Input Pulldown Resistor
844101AGI-312
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REV.A NOVEMBER 28, 2005
3
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 4A. OE CONTROL INPUT FUNCTION TABLE
Input
OE
0
Outputs
Q, nQ
HiZ
1
Enabled
TABLE 4B. SEL CONTROL INPUT FUNCTION TABLE
Input
SEL
0
Selected Source
XTAL_IN, XTAL_OUT
CLK
1
TABLE 4C. MODE CONTROL INPUT FUNCTION TABLE
Input
Mode
0
Condition
Q, nQ
Default Mode
1
Frequency Margining Mode
TABLE 4D. SERIAL MODE FUNCTION TABLE
Inputs
Conditions
S_LOAD S_CLOCK
S_DATA
L
H
↓
X
↑
L
X
Serial inputs are ignored.
Serial input mode.
Data
X
Shift register is loaded with data on S_DATA on each rising edge of S_CLOCK.
Contents of the shift register are latched.
NOTE: L = LOW
H = HIGH
X = Don't care
↑ = Rising edge transition
↓= Falling edge transition
844101AGI-312
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REV.A NOVEMBER 28, 2005
4
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
DD
Inputs, V
-0.5V to VDD + 0.5V
I
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
Package Thermal Impedance, θJA 89°C/W (0 lfpm)
Storage Temperature, T -65°C to 150°C
STG
TABLE 5A. POWER SUPPLY DC CHARACTERISTICS, VDD =VDDA =VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
3.135
3.3
3.3
3.3
85
7
3.465
3.465
3.465
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
19
TABLE 5B. POWER SUPPLY DC CHARACTERISTICS, VDD =VDDA = 3.3V 5%,VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical
Maximum Units
VDD
VDDA
VDDO
IDD
Core Supply Voltage
3.135
3.135
2.375
3.3
3.3
2.5
85
7
3.465
3.465
2.625
V
V
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
V
mA
mA
mA
IDDA
IDDO
18
844101AGI-312
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REV.A NOVEMBER 28, 2005
5
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 5C. LVCMOS / LVTTL DC CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
VDD = 3.3V
VDD = 3.3V
2
VCC + 0.3
0.8
V
V
Input Low Voltage
-0.3
CLK, SEL,
S_LOAD, S_CLOCK,
S_DATA, MODE
VDD = VIN = 3.465
150
5
µA
µA
Input
High Current
IIH
OE
V
DD = VIN = 3.465
VDD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
CLK, SEL,
S_LOAD, S_CLOCK,
S_DATA, MODE
-5
µA
Input
Low Current
IIL
OE
V
-150
µA
OE, SEL, S_CLOCK,
S_DATA, S_LOAD,
MODE
Input Transistion
Rise/Fall Rate
Δt/Δv
20
ns/v
TABLE 5D. LVDS DC CHARACTERISTICS, VDD = VDDA = VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter Test Conditions Minimum
Typical
375
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
40
1.42
50
Δ VOS
VOS Magnitude Change
mV
TABLE 5E. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V 5%, VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
365
Maximum Units
VOD
Differential Output Voltage
mV
mV
V
Δ VOD
VOS
VOD Magnitude Change
Offset Voltage
40
1.37
50
Δ VOS
VOS Magnitude Change
mV
TABLE 6. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum Units
Mode of Oscillation
Frequency
Fundamental
25
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
50
7
pF
100
µW
NOTE: Characterized using an 18pF parallel resonant crystal.
844101AGI-312
www.icst.com/products/hiperclocks.html
REV.A NOVEMBER 28, 2005
6
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 7. INPUT FREQUENCY CHARACTERISTICS, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
CLK
25
25
MHz
MHz
MHz
Input
fIN
XTAL_IN/XTAL_OUT
S_CLOCK
Frequency
50
TABLE 8A. AC CHARACTERISTICS, VDD =VDDA =VDDO = 3.3V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fOUT
Output Frequency
312.5
MHz
Mode = LOW
312.5MHz, (1.875MHz - 20MHz)
tjit(Ø)
RMS Phase Jitter; NOTE 1
Output Rise/Fall Time
0.52
ps
tR / tF
odc
20% to 80%
360
50
ps
%
Output Duty Cycle
S_DATA to
10
10
10
ns
ns
ns
S_CLOCK
S_CLOCK
tS
Setup Time
to S_LOAD
S_DATA to
S_CLOCK
tH
Hold Time
NOTE 1: Characterized using a 25MHz crystal.
TABLE 8B. AC CHARACTERISTICS, VDD = VDDA = 3.3V 5%,VDDO = 2.5V 5%, TA = -40°C TO 85°C
Symbol Parameter
Test Conditions
Minimum
Typical
Maximum Units
fOUT
Output Frequency
312.5
MHz
Mode = LOW
312.5MHz, (1.875MHz - 20MHz)
tjit(Ø)
RMS Phase Jitter; NOTE 1
Output Rise/Fall Time
0.50
ps
tR / tF
odc
20% to 80%
375
50
ps
%
Output Duty Cycle
S_DATA to
10
10
10
ns
ns
ns
S_CLOCK
S_CLOCK
tS
Setup Time
to S_LOAD
S_DATA to
S_CLOCK
tH
Hold Time
NOTE 1: Characterized using a 25MHz crystal.
844101AGI-312
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REV.A NOVEMBER 28, 2005
7
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
3.3V
2.5V
3.3V
SCOPE
Qx
SCOPE
Qx
+ +
–
LVDS
POWER
SUPPLY
Float GND
Power Supply
Float GND
LVDS
+
-
nQx
nQx
3.3V CORE/3.3V OUTPUT LOAD ACTEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD ACTEST CIRCUIT
Phase Noise Plot
nQ
Q
tPW
Phase Noise Mask
tPERIOD
tPW
odc =
x 100%
Offset Frequency
tPERIOD
f1
f2
RMS Jitter = Area Under the Masked Phase Noise Plot
RMS PHASE JITTER
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
VDD
80%
tF
80%
tR
out
out
VSWING
20%
➤
Clock
Outputs
20%
DC Input
LVDS
VOS/Δ VOS
➤
OUTPUT RISE/FALLT IME
OFFSETVOLTAGE SETUP
VDD
➤
out
out
LVDS
DC Input
100
V
OD/Δ VOD
➤
DIFFERENTIAL OUTPUT VOLTAGE SETUP
844101AGI-312
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REV.A NOVEMBER 28, 2005
8
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise. The ICS844101I-312 pro-
vides separate power supplies to isolate any high switch-
ing noise from the outputs to the internal PLL. VDD, VDDA, and
VDDO should be individually connected to the power supply
plane through vias, and bypass capacitors should be
used for each pin. To achieve optimum jitter performance,
power supply isolation is required. Figure 2 illustrates how
a 10Ω resistor along with a 10µF and a .01μF bypass
capacitor should be connected to each VDDA. The 10Ω resis-
tor can also be replaced by a ferrite bead.
3.3V
VDD
.01μF
.01μF
10Ω
VDDA
10μF
FIGURE 2. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
The ICS844101I-312 has been characterized with 18pF
parallel resonant crystals. The capacitor values shown in
Figure 3 below were determined using a 25MHz, 18pF
parallel resonant crystal and were chosen to minimize the
ppm error.
XTAL_OUT
XTAL_IN
C1
27p
X1
18pF Parallel Crystal
C2
27p
Figure 3. CRYSTAL INPUt INTERFACE
844101AGI-312
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REV.A NOVEMBER 28, 2005
9
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
RECOMMENDATIONS FOR UNUSED INPUT PINS
INPUTS:
CRYSTAL INPUT:
LVCMOS CONTROL PINS:
For applications not requiring the use of the crystal oscillator All control pins have internal pull-ups or pull-downs; additional
input, both XTAL_IN and XTAL_OUT can be left floating. resistance is not required but can be added for additional
Though not required, but for additional protection, a 1kΩ protection. A 1kΩ resistor can be used.
resistor can be tied from XTAL_IN to ground.
CLK INPUT:
For applications not requiring the use of the test clock, it can
be left floating. Though not required, but for additional
protection, a 1kΩ resistor can be tied from the CLK input to
ground.
3.3V, 2.5V LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 4. In a 100Ω
differential transmission line environment, LVDS drivers
require a matched load termination of 100Ω across near
the receiver input. For a multiple LVDS outputs buffer, if only
partial outputs are used, it is recommended to terminate the
unused outputs.
2.5V or 3.3V
VDD
LVDS_Driv er
+
R1
100
-
100 Ohm Differential Transmission Line
FIGURE 4. TYPICAL LVDS DRIVERT ERMINATION
844101AGI-312
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REV.A NOVEMBER 28, 2005
10
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
RELIABILITY INFORMATION
TABLE 9. θJAVS. AIR FLOW TABLE FOR 16 LEAD TSSOP
θJA byVelocity (Linear Feet per Minute)
0
200
118.2°C/W
81.8°C/W
500
106.8°C/W
78.1°C/W
Single-Layer PCB, JEDEC Standard Test Boards
Multi-Layer PCB, JEDEC Standard Test Boards
137.1°C/W
89.0°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS844101I-312 is: 4093
844101AGI-312
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REV.A NOVEMBER 28, 2005
11
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PACKAGE OUTLINE - G SUFFIX FOR 16 LEADTSSOP
TABLE 10. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
16
--
1.20
0.15
1.05
0.30
0.20
5.10
A1
A2
b
0.05
0.80
0.19
0.09
4.90
c
D
E
6.40 BASIC
0.65 BASIC
E1
e
4.30
4.50
L
0.45
0°
0.75
8°
α
aaa
--
0.10
Reference Document: JEDEC Publication 95, MO-153
844101AGI-312
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REV.A NOVEMBER 28, 2005
12
PRELIMINARY
ICS844101I-312
Integrated
Circuit
Systems, Inc.
FEMTOCLOCKS™ C RYSTAL-TO-LVDS
312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE 11. ORDERING INFORMATION
Part/Order Number
ICS844101AGI-312
Marking
TBD
Package
Shipping Packaging Temperature
16 Lead TSSOP
tube
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
-40°C to 85°C
ICS844101AGI-312T
ICS844101AGI-312LF
ICS844101AGI-312LFT
TBD
16 Lead TSSOP
2500 tape & reel
tube
TBD
16 Lead "Lead-Free" TSSOP
16 Lead "Lead-Free" TSSOP
TBD
2500 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS complaint.
The aforementioned trademarks, HiPerClockS and FemtoClocks are trademarks of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial and industrial applications. Any other applications such as those requiring high reliability or other extraordinary environmental requirements are not recommended without
additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS product for use in life support devices or critical
medical instruments.
844101AGI-312
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REV.A NOVEMBER 28, 2005
13
相关型号：
ICS844202BK-245LF
Clock Generator, 5 X 5 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32
IDT
ICS844204BK-245LF
Clock Generator, 250MHz, 5 X 5 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32
IDT
ICS844204BK-245LFT
Clock Generator, 250MHz, 5 X 5 MM, 0.75 MM HEIGHT, ROHS COMPLIANT, MO-220VHHD-2, VFQFN-32
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ICS844242AGI-04LF
Clock Generator, 150MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
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ICS844242AGI-04LFT
Clock Generator, 150MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
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ICS844242AGI-08LF
Clock Generator, 75MHz, PDSO16, 4.40 X 5 MM, 0.92 MM HEIGHT, ROHS COMPLIANT, MO-153, TSSOP-16
IDT
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