ICS84427CMT [ICSI]
CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER; CRYSTAL - TO- LVDS集成的频率合成/扇出缓冲器
| 型号： | ICS84427CMT |
| 厂家： | 
INTEGRATED CIRCUIT SOLUTION INC |
| 描述： | CRYSTAL-TO-LVDS INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER |
| 文件： | 总13页 (文件大小：130K) |
| 中文： | 中文翻译 | 下载： | 下载PDF数据表文档文件 |
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
GENERAL DESCRIPTION
FEATURES
The ICS84427 is a Crystal-to-LVDS Frequency • Six LVDS outputs
ICS
HiPerClockS™
Synthesizer/Fanout Buffer and a member of the
• Crystal oscillator interface
HiPerClockS™family of High Performance Clock
Solutions from ICS. The output frequency can be
programmed using the frequency select pins. The
• Output frequency range: 77.76MHz to 625MHz
• Crystal input frequency: 19.44MHz, 25MHz or 25.5MHz
low phase noise characteristics of the ICS84427 make it an
ideal clock source for 10 Gigabit Ethernet, 10 Gigabit Fibre
Channel, OC3 and OC12 applications.
• RMS phase jitter at 155.52MHz, using a 19.44MHz crystal
(12kHz to 20MHz): 3.4ps (typical)
Phase noise:
Offset
Noise Power
100Hz ................. -95 dBc/Hz
1kHz ............... -110 dBc/Hz
10kHz ............... -120 dBc/Hz
100kHz ............... -121 dBc/Hz
FUNCTION TABLE
Output
Frequency
Inputs
F_XTAL MR F_SEL2 F_SEL1 F_SEL0
F_OUT
LOW
• 3.3V supply voltage
X
1
0
0
0
0
0
0
0
0
0
X
1
1
1
1
0
0
0
0
0
X
0
0
1
1
0
0
1
1
0
X
0
1
0
1
0
1
0
1
1
• 0°C to 70°C ambient operating temperature
• Industrial temperature information available upon request
19.44MHz
19.44MHz
19.44MHz
19.44MHz
25MHz
77.76MHz
155.52MHz
311.04MHz
622.08MHz
78.125MHz
156.25MHz
312.5 MHz
625MHz
• Available in both standard and lead-free RoHS-compliant
packages
25MHz
25MHz
25MHz
25.5MHz
159.375MHz
BLOCK DIAGRAM
PIN ASSIGNMENT
Q0
nQ0
Q1
nQ1
Q2
nQ2
Q3
nQ3
Q4
1
2
3
4
24
23
22
21
20
19
18
VDD
F_SEL0
F_SEL1
MR
XTAL_IN
XTAL_OUT
F_SEL2
VDDA
VDD
PLL_SEL
GND
XTAL_IN
OSC
XTAL_OUT
6
Q0:Q5
0
1
/
Output
Divider
5
6
7
8
6
/
nQ0:nQ5
PLL
17
16
15
14
13
9
10
11
12
nQ4
Q5
nQ5
Feedback
Divider
VDD
ICS84427
24-Lead, 300-MIL SOIC
7.5mm x 15.33mm x 2.3mm body package
M Package
TopView
F_SEL2 MR PLL_SEL
F_SEL1
F_SEL0
The Preliminary Information presented herein represents a product in prototyping or pre-production.The noted characteristics are based on initial
product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves the right to change any circuitry or specifications without notice.
84427CM
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REV.D NOVEMBER 30, 2005
1
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
TABLE 1. PIN DESCRIPTIONS
Number
1, 2
Name
Q0, nQ0
Q1, nQ1
Q2, nQ2
Q3, nQ3
Q4, nQ4
Q5, nQ5
VDD
Type
Description
Output
Output
Output
Output
Output
Output
Power
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Differential output pair. LVDS interface levels.
Core supply pins.
3, 4
5, 6
7, 8
9, 10
11, 12
13, 16, 24
14
GND
Power supply ground.
Selects between the PLL and crystal inputs as the input to the dividers.
When HIGH, selects PLL. When LOW, selects XTAL_IN and
XTAL_OUT. LVCMOS / LVTTL interface levels.
15
PLL_SEL
Input
Pullup
17
18
VDDA
Power
Input
Analog supply pin.
F_SEL2
Pullup
Feedback frequency select pin. LVCMOS/LVTTL interface levels.
19,
20
XTAL_OUT,
XTAL_IN
Crystal oscillator interface. XTAL_IN is the input,
XTAL_OUT is the output.
Input
Active High Master Reset. When logic HIGH, the internal dividers are
reset causing the true outputs Qx to go low and the inverted outputs
nQx to go high. When logic LOW, the internal dividers and the outputs
are enabled. LVCMOS / LVTTL interface levels.
21
MR
Input Pulldown
22
23
F_SEL1
F_SEL0
Input Pulldown Output frequency select pin. LVCMOS/LVTTL interface levels.
Input Pullup Output frequency select pin. LVCMOS/LVTTL interface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
TABLE 2. PIN CHARACTERISTICS
Symbol
CIN
Parameter
Test Conditions
Minimum Typical Maximum Units
Input Capacitance
Input Pullup Resistor
4
pF
kΩ
kΩ
RPULLUP
51
51
RPULLDOWN Input Pulldown Resistor
84427CM
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REV.D NOVEMBER 30, 2005
2
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
ABSOLUTE MAXIMUM RATINGS
SupplyVoltage, V
4.6V
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
DD
Inputs, V
-0.5V to VDD + 0.5V
I
device.These ratings are stress specifications only.Functional
operation of product at these conditions or any conditions be-
yond those listed in the DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
Outputs, IO
Continuous Current
Surge Current
10mA
15mA
PackageThermal Impedance, θ
50°C/W (0 lfpm)
-65°C to 150°C
JA
StorageTemperature, T
STG
TABLE 3A. POWER SUPPLY DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum
3.135
Typical
3.3
Maximum Units
VDD
VDDA
IDD
Core Supply Voltage
3.465
3.465
V
Analog Supply Voltage
Power Supply Current
Analog Supply Current
3.135
3.3
V
235
20
mA
mA
IDDA
TABLE 3B. LVCMOS / LVTTL DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
VIH
VIL
Input High Voltage
2
VDD + 0.3
V
Input Low Voltage
-0.3
0.8
150
5
V
MR, F_SEL1
VDD = VIN = 3.465V
µA
µA
µA
µA
IIH
Input High Current
PLL_SEL, F_SEL0
MR, F_SEL1
V
DD = VIN = 3.465V
VDD = 3.465V, VIN = 0V
DD = 3.465V, VIN = 0V
-5
IIL
Input Low Current
PLL_SEL, F_SEL0
V
-150
TABLE 3C. LVDS DC CHARACTERISTICS, VDD = VDDA = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol
VOD
Parameter
Test Conditions
Minimum
Typical
Maximum Units
Differential Output Voltage
VOD Magnitude Change
Offset Voltage
250
400
600
50
mV
mV
V
Δ VOD
VOS
1.4
Δ VOS
VOS Magnitude Change
50
mV
84427CM
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REV.D NOVEMBER 30, 2005
3
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
TABLE 4. CRYSTAL CHARACTERISTICS
Parameter
Test Conditions
Minimum Typical Maximum
Units
Mode of Oscillation
Frequency
Fundamental
19.44
25.5
50
7
MHz
Ω
Equivalent Series Resistance (ESR)
Shunt Capacitance
Drive Level
pF
1
mW
TABLE 5. AC CHARACTERISTICS, VCC = VCCA = 3.3V 5ꢀ, TA = 0°C TO 70°C
Symbol Parameter
Test Conditions
Minimum Typical Maximum Units
FOUT
Output Frequency
77.76
625
MHz
RMS Phase Jitter (Random);
NOTE 1
155.52MHz,
(Integration Range: 12kHz-20MHz)
tjit(Ø)
3.4
ps
tsk(o)
tR / tF
odc
Output Skew; NOTE 2, 3
Output Rise/Fall Time
Output Duty Cycle
PLL Lock Time
40
400
50
ps
ps
ꢀ
20ꢀ to 80ꢀ
45
55
1
tLOCK
ms
See Parameter Measurement Information section.
NOTE 1: See Phase Noise Plots.
NOTE 2: Defined as skew between outputs at the same supply voltage and with equal load conditions.
Measured at the output differential crossing points.
NOTE 3: This parameter is defined in accordance with JEDEC Standard 65.
84427CM
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REV.D NOVEMBER 30, 2005
4
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
TYPICAL PHASE NOISE AT 155.52MHZ
0
-10
19.44MHz Input
RMS Phase Noise Jitter
-20
12kHz to 20MHz = 3.4ps (typical)
-30
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (HZ)
TYPICAL PHASE NOISE AT 156.25MHZ
0
-10
-20
-30
25MHz Input
RMS Phase Noise Jitter
12kHz to 20MHz = 3.1ps (typical)
-40
-50
-60
-70
-80
-90
-100
-110
-120
-130
-140
-150
-160
-170
-180
-190
10
100
1k
10k
100k
1M
10M
OFFSET FREQUENCY (HZ)
84427CM
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REV.D NOVEMBER 30, 2005
5
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
VDD
out
out
SCOPE
Qx
➤
3.3V 5ꢀ
DC Input
LVDS
POWER SUPPLY
+
LVDS
Float GND
-
nQx
VOS/Δ VOS
➤
3.3V OUTPUT LOAD AC TEST CIRCUIT
OFFSETVOLTAGE SETUP
VDD
nQx
Qx
➤
out
LVDS
DC Input
100
V
OD/Δ VOD
nQy
➤
Qy
out
tsk(o)
DIFFERENTIAL OUTPUT VOLTAGE SETUP
OUTPUT SKEW
nQ0:nQ5
Q0:Q5
80ꢀ
tF
80ꢀ
VOD
tPW
Clock
20ꢀ
20ꢀ
tPERIOD
Outputs
tR
tPW
odc =
x 100ꢀ
tPERIOD
OUTPUT RISE/FALL TIME
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
84427CM
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REV.D NOVEMBER 30, 2005
6
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
As in any high speed analog circuitry, the power supply pins
are vulnerable to random noise.The ICS84427 provides sepa-
rate power supplies to isolate any high switching
noise from the outputs to the internal PLL.VDD and VDDA should
be individually connected to the power supply plane through
vias, and bypass capacitors should be used for each pin. To
achieve optimum jitter performance, power supply isolation is
required. Figure 1 illustrates how a 24Ω resistor along with a
10μF and a .01μF bypass capacitor should be connected to
each VDDA pin.
3.3V
VDD
.01μF
.01μF
24Ω
VDDA
10 μF
FIGURE 1. POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
parallel resonant crystal and were chosen to minimize the
ppm error. The optimum C1 and C2 values can be slightly
adjusted for different board layouts.
The ICS84427 has been characterized with 18pF parallel
resonant crystals. The capacitor values, C1 and C2, shown
in Figure 2 below were determined using a 25MHz, 18pF
XTAL_IN
C1
18p
X1
18pF Parallel Crystal
XTAL_OUT
C2
22p
Figure 2. CRYSTAL INPUt INTERFACE
84427CM
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REV.D NOVEMBER 30, 2005
7
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
LVDS DRIVER TERMINATION
A general LVDS interface is shown in Figure 3. In a 100Ω differ- put. For a multiple LVDS outputs buffer, if only partial outputs
ential transmission line environment, LVDS drivers require a are used, it is recommended to terminate the un-used outputs.
matched load termination of 100Ω across near the receiver in-
3.3V
3.3V
LVDS_Driver
+
R1
100
-
100 Ohm Differiential Transmission Line
FIGURE 3. TYPICAL LVDS DRIVER TERMINATION
RECOMMENDATIONS FOR UNUSED OUTPUT PINS
OUTPUTS:
LVDS
All unused LVDS output pairs can be either left floating or
terminated with 100Ω across. If they are left floating, we
recommend that there is no trace attached.
84427CM
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REV.D NOVEMBER 30, 2005
8
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
SCHEMATIC EXAMPLE
Figure 4A shows a schematic example of using an ICS84427. In
this example, the input is a 25MHz parallel resonant crystal with
load capacitor CL=18pF. The frequency fine tuning capacitors
C1 and C2 is 22pF and 18pF respectively. This example also
shows logic control input handling. The configuration is set at
F_SEL[2:0]=101, therefore, the output frequency is 156.25MHz.
It is recommended to have one decouple capacitor per power
pin. Each decoupling capacitor should be located as close as
possible to the power pin.The low pass filter R7, C11 and C16 for
clean analog supply should also be located as close to the VDDA
pin as possible.For LVDS driver, the unused output pairs should
be terminated with a 100Ω resistor across.
VDD
U1
VDD
R4
1K
VDD
Zo = 50
13
14
15
16
17
18
19
20
21
22
23
24
12
VDD
VEE
nQ5
Q5
nQ4
Q4
nQ3
Q3
nQ2
Q2
nQ1
Q1
nQ0
Q0
+
-
R7
24
11
10
9
8
7
6
5
4
3
PLL_SEL
VDD
VDDA
F_SEL2
XTAL_OU T
XTAL_IN
MR
F_SEL1
F_SEL0
VDD
R1
100
VDDA
22p
F_SEL2
C11
0.1u
C16
10u
C1
Zo = 50
LVDS_input
F_SEL1
F_SEL0
X1
25MHz,18pF
R5
1K
2
1
C2
VDD
VDD
18p
ICS84427
RU1
1K
RU2
SP
RU3
1K
VDD=3.3V
F_SEL2
F_SEL1
F_SEL0
VDD
(U1,13)
(U1,16)
(U1,24)
C6
0.1u
C5
0.1u
C3
0.1u
e.g. F_SEL[2:0]=101
RD1
SP
RD2
1K
RD3
SP
SP = Spare, Not Installed
FIGURE 4A. ICS84427 SCHEMATIC EXAMPLE
84427CM
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REV.D NOVEMBER 30, 2005
9
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
• The differential 100Ω output traces should have the
same length.
The following component footprints are used in this layout
example:
• Avoid sharp angles on the clock trace. Sharp angle
turns cause the characteristic impedance to change
on the transmission lines.
All the resistors and capacitors are size 0603.
POWER AND GROUNDING
Place the decoupling capacitors C3, C5 and C6, as close as
possible to the power pins. If space allows, placement of the
decoupling capacitor on the component side is preferred. This
can reduce unwanted inductance between the decoupling ca-
pacitor and the power pin caused by the via.
• Keep the clock traces on the same layer. Whenever
possible, avoid placing vias on the clock traces. Place-
ment of vias on the traces can affect the trace charac-
teristic impedance and hence degrade signal integ-
rity.
• To prevent cross talk, avoid routing other signal traces
in parallel with the clock traces. If running parallel traces
is unavoidable, allow a separation of at least three
trace widths between the differential clock trace and
the other signal trace.
Maximize the power and ground pad sizes and number of vias
capacitors.This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed
as close to the VDDA pin as possible.
• Make sure no other signal traces are routed between
the clock trace pair.
CLOCK TRACES AND TERMINATION
• The matching termination resistors should be located as
close to the receiver input pins as possible.
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the board
and the component location.While routing the traces, the clock
signal traces should be routed first and should be locked prior to
routing other signal traces.
CRYSTAL
The crystal X1 should be located as close as possible to the pins
20 (XTAL_IN) and 19 (XTAL_OUT). The trace length between
the X1 and U1 should be kept to a minimum to avoid unwanted
parasitic inductance and capacitance. Other signal traces
should not be routed near the crystal traces.
C6
GND
VDD
C1
C5
Signals
VIA
R7
VDDA
C16
C11
X1
C3
C2
50 Ohm Traces
Pin1
U1 ICS84427
FIGURE 4B. PCB BOARD LAYOUT FOR ICS84427
84427CM
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REV.D NOVEMBER 30, 2005
10
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
RELIABILITY INFORMATION
TABLE 7. θJAVS. AIR FLOW TABLE FOR 24 LEAD SOIC
θJA byVelocity (Linear Feet per Minute)
0
200
43°C/W
500
38°C/W
Multi-Layer PCB, JEDEC Standard Test Boards
50°C/W
NOTE: Most modern PCB designs use multi-layered boards.The data in the second row pertains to most designs.
TRANSISTOR COUNT
The transistor count for ICS84427 is: 2804
84427CM
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REV.D NOVEMBER 30, 2005
11
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
PACKAGE OUTLINE - M SUFFIX FOR 24 LEAD SOIC
TABLE 8. PACKAGE DIMENSIONS
Millimeters
Minimum Maximum
SYMBOL
N
A
24
--
2.65
--
A1
A2
B
0.10
2.05
0.33
0.18
15.20
7.40
2.55
0.51
0.32
15.85
7.60
C
D
E
e
1.27 BASIC
H
h
10.00
0.25
0.40
0°
10.65
0.75
1.27
8°
L
α
Reference Document: JEDEC Publication 95, MS-013, MO-119
84427CM
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REV.D NOVEMBER 30, 2005
12
PRELIMINARY
ICS84427
Integrated
Circuit
Systems, Inc.
CRYSTAL-TO-LVDS
INTEGRATED FREQUENCY SYNTHESIZER/FANOUT BUFFER
TABLE 9. ORDERING INFORMATION
Part/Order Number
Marking
Package
Shipping Packaging
tube
Temperature
0°C to 70°C
0°C to 70°C
0°C to 70°C
0°C to 70°C
ICS84427CM
ICS84427CMT
ICS84427CMLF
ICS84427CMLFT
ICS84427CM
ICS84427CM
24 Lead SOIC
24 Lead SOIC
1000 tape & reel
tube
ICS84427CMLF
ICS84427CMLF
24 Lead "Lead-Free" SOIC
24 Lead "Lead-Free" SOIC
1000 tape & reel
NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS complaint.
The aforementioned trademark, HiPerClockS is a trademark of Integrated Circuit Systems, Inc. or its subsidiaries in the United States and/or other countries.
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Incorporated (ICS) assumes no responsibility for either its use
or for infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements are
not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any ICS
product for use in life support devices or critical medical instruments.
84427CM
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REV.D NOVEMBER 30, 2005
13
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Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137DB
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9137LG
Multi-Output, Sequence Selectable Power-Supply Controller for Mobile ApplicationsWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
SI9122E
500-kHz Half-Bridge DC/DC Controller with Integrated Secondary Synchronous Rectification DriversWarning: Undefined variable $rtag in /www/wwwroot/website_ic37/www.icpdf.com/pdf/pdf/index.php on line 217
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VISHAY
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